External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

ID 772632
Date 12/04/2023
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Document Table of Contents
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3.1. Synthesis Design Example

The synthesis design example contains the major blocks shown in the figure below.
  • A traffic generator, which is a synthesizable AXI4 driver that implements a hard-coded pattern. The traffic generator also monitors the data read from the memory to ensure it matches the written data and asserts a failure otherwise.
    • Single write and read (with AxLEN=axlen_a 1 )
    • Single write and read (with AxLEN=axlen_b 2 )
    • Sequential address 3 block of 512 writes and 512 reads (with AxLEN=axlen_a 1 )
    • Sequential address 3 block of 512 writes and 512 reads (with AxLEN=axlen_b 2 )
    • Random address 4 block of 512 writes and 512 reads (with AxLEN= axlen_a 1 )
    1 The axlen_a value is dependent on the memory technology:
    • For DDR4: 0
    • For DDR5: 1
    • For LPDDR5: 3
    2 The axlen_b value is dependent on the memory technology:
    • For DDR4: 0
    • For DDR5: 0 (results in Read-Modify-Write or Data-Masking on the memory side).
    • For LPDDR5: 3
    3 Sequential Address pattern starts at address=0, and increments by (AXI_DATA_WIDTH/8)*(AxLEN+1) on each transaction.
    4 Random Address pattern starts at address=0, and uses pseudo-random addresses.
  • An instance of the memory interface, which includes:
    • A memory controller which implements all the memory commands and protocol-level requirements.
    • The PHY, which serves as an interface between the memory controller and external memory devices to perform read and write operations.
Figure 37. Synthesis Design Example Sync Fabric Mode

Synthesis Example Design

Figure 38. Synthesis Design Example Async Fabric Mode
Figure 39. Synthesis Design Example NoC Fabric Mode