External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

Download PDF
ID 772632
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 4. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Intel Agilex® 7 M-Series EMIF IP 2.7. Compiling the Intel Agilex® 7 M-Series EMIF Design Example 2.8. Generating the EMIF Design Example with the Performance Monitor
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.1. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.3. Generating a Custom Memory Preset File for DDR5 2.1.1.3.4. Guidelines for Selecting the DDR5 DRAM Component Package Type 2.1.1.3.5. Generating a Custom Memory Preset File for LPDDR5
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel Agilex® 7 M-Series EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface 2.3.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width 2.3.3. Combining Pin and Byte Swizzling Example : Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for a x32 + ECC interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

2.3.3. Combining Pin and Byte Swizzling

Example : Combining Pin and Byte Swizzling

This example combines the two previous examples, entering the following swizzle parameters:

  • PIN_SWIZZLE_CH0_DQS0=3,1,2,0,4,7,5,6;
  • PIN_SWIZZLE_CH0_DQS2=16,23,18,19,20,21,22,17;
  • BYTE_SWIZZLE_CH0=2,X,X,X,1,0,3,X;

The following table shows the resulting pin placement after DQ pin and byte swizzling.

Table 9.  Example of resulting pin placement after DQ pin and byte swizzling
Lane Pin Index Default Effective Pinout
BL5 71 MEM_DQ[23] MEM_DQ[6]
70 MEM_DQ[22] MEM_DQ[5]
69 MEM_DQ[21] MEM_DQ[7]
68 MEM_DQ[20] MEM_DQ[4]
67    
66 MEM_DM_N[2] MEM_DM_N[0]
65 MEM_DQS_C[2] MEM_DQS_C[0]
64 MEM_DQS_T[2] MEM_DQS_T[0]
63 MEM_DQ[19] MEM_DQ[0]
62 MEM_DQ[18] MEM_DQ[2]
61 MEM_DQ[17] MEM_DQ[1]
60 MEM_DQ[16] MEM_DQ[3]
BL0 11 MEM_DQ[7] MEM_DQ[17]
10 MEM_DQ[6] MEM_DQ[22]
9 MEM_DQ[5] MEM_DQ[21]
8 MEM_DQ[4] MEM_DQ[20]
7    
6 MEM_DM_N[0] MEM_DM_N[2]
5 MEM_DQS_C[0] MEM_DQS_C[2]
4 MEM_DQS_T[0] MEM_DQS_T[2]
3 MEM_DQ[3] MEM_DQ[19]
2 MEM_DQ[2] MEM_DQ[18]
1 MEM_DQ[1] MEM_DQ[23]
0 MEM_DQ[0] MEM_DQ[16]
Note:

When using the EMIF IP with 2 channels , the syntax for CH0 and CH1 must be the following:

  • PIN_SWIZZLE_CH0_DQS0/ PIN_SWIZZLE_CH1_DQS0
  • PIN_SWIZZLE_CH0_DQS2/ PIN_SWIZZLE_CH1_DQS2
  • BYTE_SWIZZLE_CH0/ BYTE_SWIZZLE_CH1
Level Two Title