External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

ID 772632
Date 12/04/2023
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2.4. Generating the Synthesizable EMIF Design Example

For the Intel Agilex® 7 M-Series development kit, it is sufficient to leave most of the Intel Agilex® 7 M-Series EMIF IP settings at their default values. To generate the synthesizable design example, follow these steps:
  1. On the Example Design tab, ensure that the Synthesis box is set as True.
    • If you are implementing a single interface example design, configure the EMIF IP and click File > Save to save the current settings into the IP variation file (<user instance name>.ip).
      Figure 30. Saving the Current Settings
  2. Click Generate Example Design in the upper-right corner of the window.
    Figure 31. Generate Example Design
  3. Specify a directory for the EMIF design example and click OK. Successful generation of the EMIF design example creates the synthesis file set under a qii directory.
    Figure 32. Specifying a Directory
  4. Click File > Exit to exit the IP Parameter Editor Pro window. The system prompts, Recent changes have not been generated. Generate now? Click No to continue with the next flow.
  5. To open the example design, click File > Open Project, and navigate to the <project_directory>/<design_example_name>/qii/ed_synth.qpf and click Open.
    Note: For information on compiling and programming the design example, refer to Compiling and Programming the Intel Agilex® 7 M-Series EMIF Design Example .
    Figure 33. Generated Synthesizable Design Example File Structure
Note:
  • For information on constructing a system with two or more external memory interfaces, refer to Creating a Design Example with Multiple EMIF Interfaces, in the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide.
  • For information on debugging multiple interfaces, refer to Enabling the EMIF Toolkit in an Existing Design, in the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide.
  • If you don't specify Simulation or Synthesis from the dropdown menu, the destination directory contains only Platform Designer design files, which the Intel® Quartus® Prime software cannot compile directly, but which you can view or edit in the Platform Designer. In this situation you can run the following commands to generate synthesis and simulation file sets:
    • To create an Intel® Quartus® Prime software-compilable project, run the
      quartus_sh -t make_qii_design.tcl
      script in the destination directory.
    • To create a simulation project, run the
      quartus_sh -t make_sim_design.tcl
      script in the destination directory.
  • If you have generated a design example and then make changes to it in the parameter editor, you must regenerate the design example to see your changes implemented. The newly generated design example does not overwrite the existing design example files.