Agilex™ 7 Clocking and PLL User Guide: M-Series

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ID 769001
Date 10/09/2025
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview 2. M-Series Clocking and PLL Architecture and Features 3. M-Series Clocking and PLL Design Considerations 4. Clock Control IP Core 5. IOPLL IP Core 6. I/O PLL Reconfiguration 7. Agilex™ 7 Clocking and PLL User Guide: M-Series Archives 8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: M-Series
1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. M-Series Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sectors 2.1.1.3. Programmable Clock Routing
2.1.3. Clock Control Features x
2.1.3.1. Clock Gating 2.1.3.2. Clock Divider
2.1.3.1. Clock Gating x
2.1.3.1.1. Root Clock Gate 2.1.3.1.2. Sector Clock Gate 2.1.3.1.3. I/O PLL Clock Gate 2.1.3.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Locations 2.2.4. PLL Architecture 2.2.5. PLL Control Signals 2.2.6. PLL Feedback Modes 2.2.7. Clock Multiplication and Division 2.2.8. Programmable Phase Shift 2.2.9. Programmable Duty Cycle 2.2.10. PLL Cascading 2.2.11. PLL Input Clock Switchover 2.2.12. PLL Reconfiguration and Dynamic Phase Shift 2.2.13. PLL Calibration
2.2.5. PLL Control Signals x
2.2.5.1. Reset 2.2.5.2. Locked
2.2.6. PLL Feedback Modes x
2.2.6.1. Direct Compensation Mode 2.2.6.2. LVDS Compensation Mode 2.2.6.3. Source Synchronous Compensation Mode 2.2.6.4. Normal Compensation Mode 2.2.6.5. Zero-Delay Buffer Mode 2.2.6.6. External Feedback Mode
2.2.11. PLL Input Clock Switchover x
2.2.11.1. Automatic Switchover 2.2.11.2. Automatic Switchover with Manual Override 2.2.11.3. Manual Clock Switchover
2.2.13. PLL Calibration x
2.2.13.1. Power-Up Calibration 2.2.13.2. User Calibration 2.2.13.3. Static Phase Error Calibration 2.2.13.4. Output Clock Duty Cycle Correction
3. M-Series Clocking and PLL Design Considerations x
3.1. Guidelines: Clock Switchover 3.2. Guidelines: Timing Closure 3.3. Guidelines: Resetting the PLL 3.4. Guidelines: Configuration Constraints 3.5. Clocking Constraints 3.6. IP Core Constraints 3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES IP
4. Clock Control IP Core x
4.1. Release Information for Clock Control IP 4.2. Clock Control IP Core Parameters 4.3. Clock Control IP Core Ports and Signals
5. IOPLL IP Core x
5.1. Release Information for IOPLL IP 5.2. IOPLL IP Core Parameters 5.3. IOPLL IP Core Ports and Signals
5.2. IOPLL IP Core Parameters x
5.2.1. IOPLL IP Core Parameters - PLL Tab 5.2.2. IOPLL IP Core Parameters - Settings Tab 5.2.3. IOPLL IP Core Parameters - Cascading Tab 5.2.4. IOPLL IP Core Parameters - Advanced Parameters Tab
6. I/O PLL Reconfiguration x
6.1. Implementing I/O PLL Reconfiguration using EMIF Calibration IP 6.2. Address Bus and Data Bus Settings
6.1. Implementing I/O PLL Reconfiguration using EMIF Calibration IP x
6.1.1. Release Information for EMIF Calibration IP 6.1.2. Setting Up the IOPLL IP 6.1.3. Setting Up the EMIF Calibration IP 6.1.4. Connectivity Between IOPLL FPGA IP and EMIF Calibration IP 6.1.5. Axilite Interface Ports in the EMIF Calibration IP 6.1.6. Reconfiguration Guideline for I/O PLLs 6.1.7. Design Example for I/O PLL Reconfiguration
6.1.6. Reconfiguration Guideline for I/O PLLs x
6.1.6.1. Enabling Reconfiguration for The Desired I/O PLL 6.1.6.2. Clearing off Calibration Statuses 6.1.6.3. Reconfiguring The I/O PLL 6.1.6.4. Recalibration of I/O PLL 6.1.6.5. Clock Gating (Optional)
6.1.7. Design Example for I/O PLL Reconfiguration x
6.1.7.1. Reconfiguration Option: Reconfiguration Through EMIF Calibration IP 6.1.7.2. Reconfiguration Option: Clock Gating Reconfiguration
6.2. Address Bus and Data Bus Settings x
6.2.1. Divide Settings and the Corresponding Data Bit Setting for Reconfiguration 6.2.2. Data Bus Setting for Clock Gating Reconfiguration 6.2.3. Data Bus Setting For Charge Pump Current
1. Agilex™ 7 FPGA M-Series Clocking and PLL Overview
2. M-Series Clocking and PLL Architecture and Features
3. M-Series Clocking and PLL Design Considerations
4. Clock Control IP Core
5. IOPLL IP Core
6. I/O PLL Reconfiguration
7. Agilex™ 7 Clocking and PLL User Guide: M-Series Archives
8. Document Revision History for the Agilex™ 7 Clocking and PLL User Guide: M-Series

6.2.1. Divide Settings and the Corresponding Data Bit Setting for Reconfiguration

Table 20.  Divide Settings and Corresponding Address Bus for Reconfiguration
Divide Settings Write Address Bus Setting Parameter Write Data Bus Setting Description
M Counter 0x40 Total Count data [28:20] Total count for M Counter

Bypass Enable

 data [31]
  • Data [31] =bypass enable
    • Data [31] =1,bypass is enabled. The counter is bypassed with counter division value = 1.
N Counter High Count data [7:0]
  • Data [7:0] =high_count
  • Data [16:9] =low_count
  • total_count=high_count+low_count
Low Count data [16:9]
Odd Division data [17]
  • Data [17] =Odd division
    • Data [17] =0, odd division is disabled.

      The selected counter duty cycle =

      high_count/total_count.

  • Data [17] =1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable data [8]
  • Data [8] =bypass enable
    • Data [8] =1,bypass is enabled. The counter is bypassed with counter division value = 1.
Charge Pump Current 0x44 Charge Pump Settings data [15:1]
  • Data [15:1]=Charge Pump Setting
    • Configure charge pump setting[15:1]
  • For more information about the Reconfiguration table, refer to the Multiply Factor and The Corresponding Data Bit Setting For Charge Pump Current table
C- Counters

C0 = 0x5C

C1 = 0x60

C2 = 0x64

C3 = 0x68

C4 = 0x6C

C5 = 0x70

C6 = 0x74

 High Count data [7:0]
  • Data [7:0] =high_count
  • Data [30:23] =low_count
  • total_count=high_count+low_count
Low Count data [30:23]
Odd Division data [31]
  • Data [31] =Odd division
    • Data [31] =0, odd division is disabled.

      The selected counter duty cycle =

      high_count/total_count.

  • Data [31] =1, odd division enabled. The selected counter duty cycle = (high_count– 0.5)/total_count.
Bypass Enable data [8]
  • Data [8] =bypass enable
    • Data [8] =1,bypass is enabled. The counter is bypassed with counter division value = 1.
Counter Preset data [18:11]
  • Sets the number of phase shift steps per dynamic phase shift operation. Valid range is 1 to (C-Counter Divide). Each step equals one I/O PLL VCO clock period. The default value is 1 (no phase shift). To shift by one VCO clock period, set the value to 2, and so on.
Phase Mux Preset data [21:19]
  • Specifies how many phase shifts are applied during each dynamic phase shift operation. Up to 7 steps are supported. Each step equals 1/8 of the I/O PLL VCO period.
Enable Recalibration 0x48 Permit Calibration data [14]
  • Data [14]=Enable recalibration for HVIO I/O PLL
    • Data [14]=1, to enable recalibration
Calibration 0x88 Calibration Request data [11]
  • Data [11]=Request Recalibration
    • Data [11]=1, to request recalibration
Reset 0x80 PLL Reset data [2]
  • Data [2]=Reset PLL
    • Data [2]=1,to reset PLL prior to recalibration request
Registers enablement 0x10 Enable registers data [0]
  • Data [0] = Enable registers of divide settings for read-modify-write operation.
    • Data [0]=1,to enable registers for read-modify-write operation prior to reconfiguration.
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