Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 12/01/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1. Building the Intel® Quartus® Prime Project

This design example includes prepackaged bitstreams but you can also use the build script provided to build bitstreams with custom architectures or recreate the original bitstreams, subject to IP license limitations.

The Intel® Quartus® Prime project consists of the Intel® FPGA AI Suite IP as well as IP to interface with the HPS and, in the case of the S2M variant, additional flow control IP.

Intel FPGA AI Suite SoC Design Example Quick Start Tutorial shows how to use the A10_Performance.arch configuration for the Intel® FPGA AI Suite IP, but you can use any other Intel® Arria® 10 configuration file instead.