7.4. MMD Layer Hardware Interaction Library
Runtime communication with CSR registers for the stream controller and for the Intel® FPGA AI Suite IP happens via the UIO driver. See The Userspace I/O HOWTO for more information on the UIO communication model.
Intel® FPGA AI Suite IP graph weights and instructions (from the AOT file) are transferred from host DDR memory to EMIF DDR memory (allocated to the FPGA Intel® FPGA AI Suite IP) via the mSGDMA-USERIO driver (a custom kernel driver, see Yocto Recipe: recipes-drivers/msgdma-userio/msgdma-userio.bb). This driver is also used to send microcode and images. Lastly, inference results are transferred into host DDR via the mSGDMA-USERIO driver.
The source files for the library are in runtime/coredla_device/mmd/hps_platform/. The files contain classes for managing and accessing the Intel® FPGA AI Suite IP, the stream controller, the layout transform module, and DMA by UIO and MSGDMA-USERIO drivers. The remainder of this section describes the key classes.