Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 2/12/2024

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.4. Top Level

After the Intel® Quartus® Prime project has finished executing, the design should look similar to the following image in the Intel® Quartus® Prime Project Navigator:
Figure 10. SoC Design Example Hierarchy
The top-level Verilog file and HPS configuration is derived directly from the GSRD designs located at

The GSRD designs have been modified to include the Intel® FPGA AI Suite IP. All unnecessary logic has been removed, which provides a concise design example.

The main Intel® FPGA AI Suite SoC design example is contained within a single Platform Designer system, called system. Double-click this node in the Intel® Quartus® Prime Project Navigator to launch Platform Designer.