Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 7/03/2023

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4.2. Compiling Exported Graphs Through the Intel® FPGA AI Suite

The network as described in the .xml and .bin files (created by the Model Optimizer) is compiled for a specific Intel® FPGA AI Suite architecture file by using the Intel® FPGA AI Suite compiler.

The Intel® FPGA AI Suite compiler compiles the network and exports it to a .bin file with the format required by the OpenVINO™ Inference Engine. For instructions on how to compile the .xml and .bin files into AOT file suitable for use with the Intel® FPGA AI Suite IP, refer to Compiling the Graphs

This .bin file created by the compiler contains the compiled network parameters for all the target devices (FPGA, CPU, or both) along with the weights and biases. The inference application imports this file at runtime.

The Intel® FPGA AI Suite compiler can also compile the graph and provide estimated area or performance metrics for a given architecture file or produce an optimized architecture file.

For the demonstration SD card, the FPGA bitstream has been built using the A10_Performance.arch IP configuration file, so use it for compiling the OpenVINO™ Model.

For more details about the Intel® FPGA AI Suite compiler, refer to the Intel® FPGA AI Suite Compiler Reference Manual .