Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 7/03/2023

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8.2. Building the Stream Controller Module

The stream controller is built as part of the steps described in Installing HPS Disk Image Build Prerequisites. For system development that extends the Intel® FPGA AI Suite SoC design example, you might want to compile the stream controller module independently.

The stream controller module source code can be found in the distribution, in the runtime/coredla_device/stream_controller/ directory.

There is a script in the source code directory that builds a binary .hex file. This file is then used by Intel® Quartus® Prime when building the firmware to embed the microcode module.

The script should be run from a Nios® V command shell, which is part of Intel® Quartus® Prime. It requires a Intel® Quartus® Prime project file and a Intel® Quartus® Prime .qsys file. For this design example, the project file is top.qpf, and the Platform Designer file is dla.qsys.

An example command to build the stream controller module is as follows:
./ top.qpf dla.qsys stream_controller.hex