Intel® FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 7/03/2023

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6.3.1. Streaming Enablement for Intel® FPGA AI Suite

In an M2M system, input buffers are provided by the host CPU. However, in a streaming system (S2M), input buffers are created by an external hardware stream. For the Intel® FPGA AI Suite IP to process this external stream, several operations must happen in a coordinated way:

  • The raw stream data must pass through a layout-transform IP core to reformat the raw data into an Intel® FPGA AI Suite compliant data format
  • The formatted data must be written into system memory at specific locations, known only to the host application and the Intel® FPGA AI Suite software library at run time.
  • The Intel® FPGA AI Suite IP job queue must be primed at the correct time, in synchronization with the input stream buffers, such that the Intel® FPGA AI Suite IP starts an inference immediately upon a new input buffer becoming ready.

Within Platform Designer, a Nios® V based subsystem is added alongside the Intel® FPGA AI Suite IP to provide the streaming capabilities. This subsystem highlighted in blue in the block diagram that follows.

In the diagram, the yellow interconnect lines indicate Avalon® streaming interfaces, and the black interconnect lines indicate memory-mapped interfaces.

Figure 8.  Nios® V Streaming Subsystem