FPGA AI Suite: IP Reference Manual

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ID 768974
Date 3/29/2024
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Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite IP Reference Manual 2. About the FPGA AI Suite IP 3. FPGA AI Suite IP Generation Utility 4. FPGA AI Suite Ahead-of-Time Splitter Utility 5. CSR Map and Descriptor Queue A. FPGA AI Suite IP Reference Manual Archives B. FPGA AI Suite IP Reference Manual Document Revision History
2. About the FPGA AI Suite IP x
2.1. Supported Models 2.2. Model Performance 2.3. FPGA AI Suite Layer / Primitive Ranges 2.4. FPGA AI Suite IP Block Configuration 2.5. IP Block Interfaces
2.1. Supported Models x
2.1.1. MobileNet V2 differences between Caffe and TensorFlow models
2.2. Model Performance x
2.2.1. Throughput on the MobileNetV1 model (and other very fast models)
2.4. FPGA AI Suite IP Block Configuration x
2.4.1. Architecture Description File Format for Instance Parameterization 2.4.2. Architecture Description File Parameters
2.4.2. Architecture Description File Parameters x
2.4.2.1. Parameter Group: Global Parameters 2.4.2.2. Parameter Group: activation 2.4.2.3. Parameter Group: pe_array 2.4.2.4. Parameter Group: pool 2.4.2.5. Parameter Group: depthwise 2.4.2.6. Module: softmax 2.4.2.7. Parameter Group: dma 2.4.2.8. Parameter Group: xbar 2.4.2.9. Parameter Group: filter_scratchpad 2.4.2.10. Parameter Group: config_network 2.4.2.11. (Early Access) Parameter Group: layout_transform_params
2.5. IP Block Interfaces x
2.5.1. Clock and Reset 2.5.2. AXI Interfaces 2.5.3. AXI Interface Clock and Reset 2.5.4. Input Feature Tensor In-Memory Format 2.5.5. Output Tensor In-Memory Format
2.5.4. Input Feature Tensor In-Memory Format x
2.5.4.1. Multiple Input Graphs 2.5.4.2. Input Folding 2.5.4.3. Input Scale and Shift 2.5.4.4. Input Transform Mapping 2.5.4.5. Input Layout Transform Hardware
3. FPGA AI Suite IP Generation Utility x
3.1. IP Generation Utility Execution Flows 3.2. IP Generation Utility Inputs 3.3. IP Generation Utility Outputs 3.4. IP Generation Utility Command Line Options
3.4. IP Generation Utility Command Line Options x
3.4.1. The --flow create_ip Flow 3.4.2. The --flow add_arch Flow 3.4.3. The --flow list Flow 3.4.4. The --flow remove_arch Flow
4. FPGA AI Suite Ahead-of-Time Splitter Utility x
4.1. Files Generated by the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.2. Building the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.3. Running the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.4. FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application
5. CSR Map and Descriptor Queue x
5.1. Discovery ROM 5.2. Interrupt Control 5.3. DMA Descriptor Queue 5.4. DMA Control Registers 5.5. Performance Registers 5.6. Debug Network Registers 5.7. DMA License Register
1. FPGA AI Suite IP Reference Manual
2. About the FPGA AI Suite IP
3. FPGA AI Suite IP Generation Utility
4. FPGA AI Suite Ahead-of-Time Splitter Utility
5. CSR Map and Descriptor Queue
A. FPGA AI Suite IP Reference Manual Archives
B. FPGA AI Suite IP Reference Manual Document Revision History

3.1. IP Generation Utility Execution Flows

The IP generation utility (dla_create_ip command) has the following flows:

Creating an IP Directory

This flow is typically first flow that you use. It creates an FPGA AI Suite IP library directory and adds an architecture as follows:

  1. Creates the IP library directory and copies all contents from <ai_suite_root>/fpga/ip_template/ into the new directory. The copied folder (<ip_template>) contains some basic Tcl scripts and Platform Designer IP configurations.
  2. Creates a <ip_directory>/Verilog directory and copies over RTL files that are common to any generated FPGA AI Suite IP architecture.

    These files are listed in static_files.tcl, which is used to ensure that other flows (the Platform Designer flow and design assembly flows outside Platform Designer) have access to the list of RTL source files.

  3. Creates the following directory for each architecture-family pair to add to the IP library:

    <ip_directory>/Verilog/<architecture>_<family>

    This location stores architecture-specific files.

  4. Invokes an internal utility to read the architecture description file (.arch).

    Output files are architecture-specific and are copied to the <ip_directory>/Verilog/<architecture>_<family> directory.

  5. For the specific architecture, creates a generated_files.tcl file and a dla_ip.qsf file in the <ip_directory>/Verilog/<architecture>_<family> directory.

Adding an Architecture to an Existing IP Directory

This flow adds a new architecture to an existing IP library directory as follows:
  1. Creates a <ip_directory >/Verilog directory and copies over RTL files that are common to any generated FPGA AI Suite IP architecture.

    These files are listed in static_files.tcl, which is used to ensure that other flows (the Platform Designer flow and design assembly flows outside Platform Designer) have access to the list of RTL source files.

  2. Creates the following directory for each architecture-family pair to add to the IP library:

    <ip_directory>/Verilog/<architecture>_<family>

    This location stores architecture-specific files.

  3. Invokes an internal utility to read the architecture description file (.arch).

    Output files are architecture-specific and are copied to the <ip_directory>/Verilog/<architecture>_<family> directory.

  4. For the specific architecture, creates a generated_files.tcl file and a dla_ip.qsf file in the <ip_directory>/Verilog/<architecture>_<family> directory.

Listing Architectures in an IP Directory

This flow lists all available architectures in the IP library directory. The utility looks for all <architecture_family> folders and displays them.

Removing an Architecture from an IP Directory

This flow removes an architecture from an IP library directory. The utility looks for a <architecture_family> folder and removes it.

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