FPGA AI Suite: IP Reference Manual

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ID 768974
Date 3/29/2024
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Document Table of Contents
Document Table of Contents x
1. FPGA AI Suite IP Reference Manual 2. About the FPGA AI Suite IP 3. FPGA AI Suite IP Generation Utility 4. FPGA AI Suite Ahead-of-Time Splitter Utility 5. CSR Map and Descriptor Queue A. FPGA AI Suite IP Reference Manual Archives B. FPGA AI Suite IP Reference Manual Document Revision History
2. About the FPGA AI Suite IP x
2.1. Supported Models 2.2. Model Performance 2.3. FPGA AI Suite Layer / Primitive Ranges 2.4. FPGA AI Suite IP Block Configuration 2.5. IP Block Interfaces
2.1. Supported Models x
2.1.1. MobileNet V2 differences between Caffe and TensorFlow models
2.2. Model Performance x
2.2.1. Throughput on the MobileNetV1 model (and other very fast models)
2.4. FPGA AI Suite IP Block Configuration x
2.4.1. Architecture Description File Format for Instance Parameterization 2.4.2. Architecture Description File Parameters
2.4.2. Architecture Description File Parameters x
2.4.2.1. Parameter Group: Global Parameters 2.4.2.2. Parameter Group: activation 2.4.2.3. Parameter Group: pe_array 2.4.2.4. Parameter Group: pool 2.4.2.5. Parameter Group: depthwise 2.4.2.6. Module: softmax 2.4.2.7. Parameter Group: dma 2.4.2.8. Parameter Group: xbar 2.4.2.9. Parameter Group: filter_scratchpad 2.4.2.10. Parameter Group: config_network 2.4.2.11. (Early Access) Parameter Group: layout_transform_params
2.5. IP Block Interfaces x
2.5.1. Clock and Reset 2.5.2. AXI Interfaces 2.5.3. AXI Interface Clock and Reset 2.5.4. Input Feature Tensor In-Memory Format 2.5.5. Output Tensor In-Memory Format
2.5.4. Input Feature Tensor In-Memory Format x
2.5.4.1. Multiple Input Graphs 2.5.4.2. Input Folding 2.5.4.3. Input Scale and Shift 2.5.4.4. Input Transform Mapping 2.5.4.5. Input Layout Transform Hardware
3. FPGA AI Suite IP Generation Utility x
3.1. IP Generation Utility Execution Flows 3.2. IP Generation Utility Inputs 3.3. IP Generation Utility Outputs 3.4. IP Generation Utility Command Line Options
3.4. IP Generation Utility Command Line Options x
3.4.1. The --flow create_ip Flow 3.4.2. The --flow add_arch Flow 3.4.3. The --flow list Flow 3.4.4. The --flow remove_arch Flow
4. FPGA AI Suite Ahead-of-Time Splitter Utility x
4.1. Files Generated by the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.2. Building the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.3. Running the FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.4. FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application
5. CSR Map and Descriptor Queue x
5.1. Discovery ROM 5.2. Interrupt Control 5.3. DMA Descriptor Queue 5.4. DMA Control Registers 5.5. Performance Registers 5.6. Debug Network Registers 5.7. DMA License Register
1. FPGA AI Suite IP Reference Manual
2. About the FPGA AI Suite IP
3. FPGA AI Suite IP Generation Utility
4. FPGA AI Suite Ahead-of-Time Splitter Utility
5. CSR Map and Descriptor Queue
A. FPGA AI Suite IP Reference Manual Archives
B. FPGA AI Suite IP Reference Manual Document Revision History

2.3. FPGA AI Suite Layer / Primitive Ranges

The following table lists the hyperparameter ranges supported by key primitive layers:

Layer / Primitive

Hyperparameter

Supported Range

Fully connected

None

n/a

2D Conv

Filter Size

Width = [1..28]

Height = [1..28]

Height does not have to equal width.

Default value for each is 14.

Stride

Maximum stride is 15

Pad

Maximum pad is (216) - 1

3D Conv Filter Size Width = [1..28]

Height = [1..28]

Depth = [1..14]

Filter volume should fit into the filter cache size.

Stride Maximum stride is 15.
Pad Maximum pad is (216) - 1

Depthwise

Filter Size

Same as 2D Conv filter size

Depth = 1

Stride

Same as 2D Conv stride

Depth = 1

Pad

Same as 2D conv padding

Depth = 1

Scale-Shift

Scale factor

FP16 float range

Bias term

FP16 float range

Deconv / Transpose Convolution

Filter Size

Any – Same as convolution, and height/width can be different

Depth = 1

Stride

1, 2, 4, 8 (stride width == stride height)

Depth = 1

Pad

Restricted to filter_[height, width] - 1

Depth = 1

ReLU

n/a

n/a

pReLU

Scaling parameter (a) (1 per filter / conv output channel)

float range

Depth = 1

Leaky ReLU

Scaling parameter (a) (1 per tensor)

float range

Clamp

Limit parameters (a, b) (1 per tensor)

float range
Round_Clamp Limit parameters (a, b) (1 per tensor) float range

H-sigmoid

n/a

n/a

H-swish

n/a

n/a
Sigmoid Slope FP16 float range
Swish Slope FP16 float range

Max Pool

Window Size

up to 7×7×7

Pad

1, 2

Stride

1, 2, 3, 4

Average Pool

Window Size

Up to 27x27 (one less than the maximum 2D convolution size)

Width == Height

Depth = 1 or 2

Pad

1, 2

Stride

1, 2, 3, 4

Softmax

Maximum Number of Channels

4096

Elementwise Multiplication of feature * filter and feature * feature tensors.2

n/a

Tensor sizes are expanded if necessary to support the multiplication.

Depth = 1
ChannelToSpace

DepthToSpace

PixelShuffle

 block_mode blocks_first or blocks_last
block_size 2, 4, 8
2 This is an element-wise multiplication, not a matrix multiply operation.
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