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2.4.2.1. Parameter Group: Global Parameters
2.4.2.2. Parameter Group: activation
2.4.2.3. Parameter Group: pe_array
2.4.2.4. Parameter Group: pool
2.4.2.5. Parameter Group: depthwise
2.4.2.6. Module: softmax
2.4.2.7. Parameter Group: dma
2.4.2.8. Parameter Group: xbar
2.4.2.9. Parameter Group: filter_scratchpad
2.4.2.10. Parameter Group: config_network
2.4.2.11. (Early Access) Parameter Group: layout_transform_params
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5.4. DMA Control Registers
Register |
Offset |
Attribute |
Description |
---|---|---|---|
Intermediate_ddr_base_address |
0x000 |
RW |
Base address for the DDR intermediate data. This is a shared address across all graphs. Only required to be set once upon startup. Must be aligned to a multiple of the DDR word size. |
Inference_completion_count |
0x004 |
RO |
Number of inference request completions by the FPGA AI Suite IP |