Nios® V Processor Software Developer Handbook

ID 743810
Date 7/20/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.1.1. Exception Handling Terminology

The following list of HAL terms outlines basic exception handling concepts:
  • Application context—The status of the Nios® V processor and the HAL during normal program execution, outside of exception funnels and handlers.
  • Context switch—The process of saving the Nios® V processor’s registers on an exception or interrupt, and restoring them on return from the exception handling routine or ISR.
  • Exception—A transfer of control away from a program’s normal flow of execution, caused by an event, either internal or external to the processor, which requires immediate attention. Exceptions include software exceptions and hardware interrupts.
  • Exception context—The status of the Nios® V processor and the HAL after a software exception or hardware interrupt, when funnel code, a software exception handler, or an ISR is executing.
  • Exception handling system—The complete system of software routines that service all exceptions, including hardware interrupts, and pass control to software exception handlers and ISRs as necessary.
  • Exception (or interrupt) latency—The time elapsed between the event that causes the exception (such as an unimplemented instruction or interrupt request) and the execution of the first instruction at the exception (or interrupt vector) address.
  • Exception (or interrupt) response time—The time elapsed between the event that causes the exception and the execution of the handler.
  • Exception overhead—Additional processing required to service a software exception or hardware interrupt, including HAL-specific processing and RTOS-specific processing if applicable.
  • Funnel code—HAL-provided code that sets up the correct processor environment for an exception-specific handler, such as an ISR.
  • Handler—Code specific to the exception type. The handler code is distinct from the funnel code, which takes care of general exception overhead tasks.
  • Implementation-dependent instruction—A Nios® V processor instruction that is not supported on all implementations of the Nios® V core. For example, the mul instructions are implementation-dependent, because they are not supported on the Nios® V/m core.
  • Interrupt—Hardware interrupt.
  • Interrupt controller—Hardware enabling the Nios® V processor to respond to an interrupt by transferring control to an ISR.
  • Interrupt request (IRQ)—Hardware interrupt.
  • Interrupt service routine (ISR)—A software routine that handles an individual hardware interrupt.
  • Invalid instruction—An instruction that is not defined for any implementation of the Nios® V processor.
  • Maskable exceptions—Exceptions that can be disabled with the mtatus.mie flag, including internal hardware interrupts, maskable external hardware interrupts, and software exceptions, but not including nonmaskable external interrupts.
  • Maximum disabled time—The maximum amount of continuous time that the system spends with maskable exceptions disabled.
  • Maximum masked time—The maximum amount of continuous time that the system spends with a single interrupt masked.
  • Miscellaneous exception—A software exception which is neither an unimplemented instruction nor a ebreak or ecall instruction.
  • Nested interrupts—The process of a high-priority interrupt taking control when a lower-priority ISR is already running.
  • Software exception—An exception caused by a software condition; that is, any exception other than a hardware interrupt. This includes unimplemented instructions and ebreak or ecall instructions.
  • Unimplemented instruction—An implementation-dependent instruction that is not supported on the particular Nios® V processor core implementation that is in your system. For example, mul instruction is unimplemented in the Nios® V/m processor core.
  • Worst-case exception (or interrupt) latency—The value of the exception (or interrupt) latency, including the maximum disabled time or maximum masked time. Including the maximum disabled or masked time accounts for the case when the exception (or interrupt) occurs at the beginning of the masked or disabled time.