Nios® V Processor Software Developer Handbook

ID 743810
Date 7/20/2023
Public

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Document Table of Contents

3.4.2.1. System Initialization

The system initialization sequence begins when the system powers up. The initialization sequence steps for FPGA designs that contain a Nios® V processor are the following:

  1. Hardware reset event: The board receives a power-on reset signal, which resets the FPGA.
  2. FPGA configuration: The FPGA is programmed with a .sof file, from a specialized configuration memory or an external hardware master.
  3. System reset: The Platform Designer system, composed of one or more Nios® V processors and other peripherals, receives a hardware reset signal and enters the components’ combined reset state.
  4. Nios V processor: Nios® V processor jumps to its preconfigured reset address and begins running instructions found at this address.
  5. Bootloader ( optional): Refer to bootloader section for more information.
  6. crt0 execution: If you used a bootloader, the processor jumps to the _entry symbol within the crt0 code. If you did not use a bootloader, the CPU starts from the _reset symbol which jumps to the_entry symbol, which is the beginning of the crt0 code.