Nios® V Processor Software Developer Handbook

ID 743810
Date 7/20/2023
Public

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Document Table of Contents

8.1.3. How the Hardware works

The Nios® V processor can respond to exceptions including hardware interrupts, timer interrupt, software interrupts and software exceptions. When the Nios® V processor responds to an exception, it performs the following tasks:
  • Disables mie bit in Machine Status Register (mstatus.mie) to save the register’s value.
  • Disables hardware interrupts by clearing mstatus.mie and saves the previous value to mstatus.mpie.
  • Saves the next execution address in Machine Exception Program Counter (mepc).
  • Transfers control to the exception address held in the Machine Trap-Vector Base-Address (mtvec) register.

All Nios® V processor exception types are precise. This means that after an exception is handled, the Nios V processor can re-execute the instruction that caused the exception.