Nios® V Embedded Processor Design Handbook

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Date 1/27/2025
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Document Table of Contents
Document Table of Contents x
1. About the Nios® V Embedded Processor 2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer 3. Nios® V Processor Software System Design 4. Nios® V Processor Configuration and Booting Solutions 5. Nios® V Processor - Using the MicroC/TCP-IP Stack 6. Nios® V Processor Debugging, Verifying, and Simulating 7. Nios® V Processor — Remote System Update 8. Nios® V Processor — Using Custom Instruction 9. Nios® V Embedded Processor Design Handbook Archives 10. Document Revision History for the Nios® V Embedded Processor Design Handbook
1. About the Nios® V Embedded Processor x
1.1. Intel® FPGA and Embedded Processors Overview 1.2. Quartus® Prime Software Support 1.3. Nios® V Processor Licensing 1.4. Embedded System Design
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer x
2.1. Creating Nios® V Processor System Design with Platform Designer 2.2. Integrating Platform Designer System into the Quartus® Prime Project 2.3. Designing a Nios® V Processor Memory System 2.4. Clocks and Resets Best Practices 2.5. Assigning a Default Agent 2.6. Assigning a UART Agent for Printing 2.7. JTAG Signals
2.1. Creating Nios® V Processor System Design with Platform Designer x
2.1.1. Instantiating Nios® V Processor Intel® FPGA IP 2.1.2. Defining System Component Design 2.1.3. Specifying Base Addresses and Interrupt Request Priorities
2.1.1. Instantiating Nios® V Processor Intel® FPGA IP x
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Intel® FPGA IP 2.1.1.2. Instantiating Nios® V/m Microcontroller Intel® FPGA IP 2.1.1.3. Instantiating Nios® V/g General Purpose Processor Intel® FPGA IP
2.1.1.1. Instantiating Nios® V/c Compact Microcontroller Intel® FPGA IP x
2.1.1.1.1. Use Reset Request Tab 2.1.1.1.2. Vectors Tab 2.1.1.1.3. ECC Tab 2.1.1.1.4. CPU Architecture Tab
2.1.1.2. Instantiating Nios® V/m Microcontroller Intel® FPGA IP x
2.1.1.2.1. Debug Tab 2.1.1.2.2. Use Reset Request Tab 2.1.1.2.3. Traps, Exceptions, and Interrupts Tab 2.1.1.2.4. CPU Architecture 2.1.1.2.5. ECC Tab
2.1.1.3. Instantiating Nios® V/g General Purpose Processor Intel® FPGA IP x
2.1.1.3.1. Debug Tab 2.1.1.3.2. Use Reset Request Tab 2.1.1.3.3. Traps, Exceptions, and Interrupts Tab 2.1.1.3.4. Memory Configurations Tab 2.1.1.3.5. Custom Instruction Tab 2.1.1.3.6. CPU Architecture 2.1.1.3.7. ECC Tab 2.1.1.3.8. Lockstep Tab
2.2. Integrating Platform Designer System into the Quartus® Prime Project x
2.2.1. Instantiating the Nios® V Processor System Module in the Quartus® Prime Project 2.2.2. Connecting Signals and Assigning Physical Pin Locations 2.2.3. Constraining the Intel FPGA Design
2.3. Designing a Nios® V Processor Memory System x
2.3.1. Volatile Memory 2.3.2. Non-Volatile Memory 2.3.3. On-Chip Memory Configuration – RAM or ROM 2.3.4. Caches 2.3.5. Tightly Coupled Memory
2.4. Clocks and Resets Best Practices x
2.4.1. System Clock 2.4.2. Reset Request Interface 2.4.3. Reset Release IP
2.4.2. Reset Request Interface x
2.4.2.1. Typical Use Cases
2.6. Assigning a UART Agent for Printing x
2.6.1. Preventing Stalls by the JTAG UART
3. Nios® V Processor Software System Design x
3.1. Nios V Processor Software Development Flow 3.2. Intel FPGA Embedded Development Tools
3.1. Nios V Processor Software Development Flow x
3.1.1. Board Support Package Project 3.1.2. Application Project
3.2. Intel FPGA Embedded Development Tools x
3.2.1. Nios® V Processor Board Support Package Editor 3.2.2. RiscFree* IDE for Intel FPGAs 3.2.3. Nios V Utilities Tools 3.2.4. File Format Conversion Tools 3.2.5. Other Utilities Tools
4. Nios® V Processor Configuration and Booting Solutions x
4.1. Introduction 4.2. Linking Applications 4.3. Nios® V Processor Booting Methods 4.4. Introduction to Nios® V Processor Booting Methods 4.5. Nios® V Processor Booting from On-Chip Flash (UFM) 4.6. Nios® V Processor Booting from General Purpose QSPI Flash 4.7. Nios® V Processor Booting from Configuration QSPI Flash 4.8. Nios® V Processor Booting from On-Chip Memory (OCRAM) 4.9. Nios® V Processor Booting from Tightly Coupled Memory (TCM) 4.10. Summary of Nios® V Processor Vector Configuration and BSP Settings 4.11. Reducing Nios® V Processor Booting Time
4.2. Linking Applications x
4.2.1. Linking Behavior
4.2.1. Linking Behavior x
4.2.1.1. Default BSP Linking 4.2.1.2. Configurable BSP Linking
4.4. Introduction to Nios® V Processor Booting Methods x
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash 4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier 4.4.3. Nios® V Processor Application Execute-In-Place from OCRAM 4.4.4. Nios® V Processor Application Execute-In-Place from TCM
4.4.1. Nios® V Processor Application Execute-In-Place from Boot Flash x
4.4.1.1. alt_load()
4.4.2. Nios® V Processor Application Copied from Boot Flash to RAM Using Boot Copier x
4.4.2.1. Nios® V Processor Bootloader via Generic Serial Flash Interface 4.4.2.2. Nios® V Processor Bootloader via Secure Device Manager
4.5. Nios® V Processor Booting from On-Chip Flash (UFM) x
4.5.1. MAX® 10 FPGA On-Chip Flash Description 4.5.2. Nios® V Processor Application Execute-In-Place from UFM 4.5.3. Nios® V Processor Application Copied from UFM to RAM using Boot Copier
4.5.2. Nios® V Processor Application Execute-In-Place from UFM x
4.5.2.1. Hardware Design Flow 4.5.2.2. Software Design Flow 4.5.2.3. Programming
4.5.3. Nios® V Processor Application Copied from UFM to RAM using Boot Copier x
4.5.3.1. Hardware Design Flow 4.5.3.2. Software Design Flow Creating the Application BSP Project Configuring the BSP Editor and Generating the BSP Project Generating the User Application Project File Building the User Application Project Generating the HEX File 4.5.3.3. Programming
4.6. Nios® V Processor Booting from General Purpose QSPI Flash x
4.6.1. Nios® V Processor Application Executes-In-Place from General Purpose QSPI Flash 4.6.2. Nios® V Processor Application Copied from General Purpose QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI)
4.6.1. Nios® V Processor Application Executes-In-Place from General Purpose QSPI Flash x
4.6.1.1. Hardware Design Flow 4.6.1.2. Software Design Flow 4.6.1.3. Programming Files Generation 4.6.1.4. QSPI Flash Programming
4.6.2. Nios® V Processor Application Copied from General Purpose QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI) x
4.6.2.1. Hardware Design Flow 4.6.2.2. Software Design Flow 4.6.2.3. Programming Files Generation 4.6.2.4. QSPI Flash Programming
4.7. Nios® V Processor Booting from Configuration QSPI Flash x
4.7.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash 4.7.2. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) 4.7.3. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices)
4.7.1. Nios® V Processor Application Executes-In-Place from Configuration QSPI Flash x
4.7.1.1. Hardware Design Flow 4.7.1.2. Software Design Flow 4.7.1.3. Programming Files Generation 4.7.1.4. QSPI Flash Programming
4.7.2. Nios V Processor Design, Configuration and Boot Flow (Control Block-based Device) x
4.7.2.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI) 4.7.2.2. Bootloader via GSFI Example Design
4.7.2.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via GSFI) x
4.7.2.1.1. Hardware Design Flow 4.7.2.1.2. Software Design Flow 4.7.2.1.3. Programming Files Generation 4.7.2.1.4. QSPI Flash Programming
4.7.3. Nios V Processor Design, Configuration and Boot Flow (SDM-based Devices) x
4.7.3.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via SDM) 4.7.3.2. Bootloader via SDM Example Design
4.7.3.1. Nios® V Processor Application Copied from Configuration QSPI Flash to RAM Using Boot Copier (Bootloader via SDM) x
4.7.3.1.1. Hardware Design Flow 4.7.3.1.2. Software Design Flow 4.7.3.1.3. Software Design Flow (Bootloader via SDM Project) 4.7.3.1.4. Software Design Flow (User Application Project) 4.7.3.1.5. Programming Files Generation 4.7.3.1.6. QSPI Flash Programming SDM
4.8. Nios® V Processor Booting from On-Chip Memory (OCRAM) x
4.8.1. Nios® V Processor Application Executes in-place from OCRAM
4.8.1. Nios® V Processor Application Executes in-place from OCRAM x
4.8.1.1. Hardware Design Flow 4.8.1.2. Software Design Flow 4.8.1.3. Programming
4.9. Nios® V Processor Booting from Tightly Coupled Memory (TCM) x
4.9.1. Nios® V Processor Application Executes in-place from TCM
4.9.1. Nios® V Processor Application Executes in-place from TCM x
4.9.1.1. Hardware Design Flow 4.9.1.2. Software Design Flow 4.9.1.3. Programming
4.11. Reducing Nios® V Processor Booting Time x
4.11.1. Boot Methods 4.11.2. Boot devices 4.11.3. Peripheral Initialization 4.11.4. Caches 4.11.5. System Speed
5. Nios® V Processor - Using the MicroC/TCP-IP Stack x
5.1. Introduction 5.2. Software Architecture 5.3. Support and Licensing 5.4. MicroC/TCP-IP Example Designs 5.5. Development Flow 5.6. Operating the Example Designs 5.7. Optional Configuration 5.8. MicroC/TCP-IP Simple Socket Server Concepts
5.4. MicroC/TCP-IP Example Designs x
5.4.1. Hardware and Software Requirements 5.4.2. Overview 5.4.3. Acquiring the Example Design Files 5.4.4. Hardware Design Files 5.4.5. Software Design Files
5.4.5. Software Design Files x
5.4.5.1. MicroC/TCP-IP IPerf Example Design 5.4.5.2. MicroC/TCP-IP Simple Socket Server Example Design
5.5. Development Flow x
5.5.1. Hardware Development Flow 5.5.2. Software Development Flow 5.5.3. Device Programming
5.5.2. Software Development Flow x
5.5.2.1. Creating a BSP project 5.5.2.2. Configuring the BSP 5.5.2.3. Creating an Application Project 5.5.2.4. Building the Application Project
5.6. Operating the Example Designs x
5.6.1. Operating the MicroC/TCP-IP IPerf 5.6.2. Operating the MicroC/TCP-IP Simple Socket Server
5.7. Optional Configuration x
5.7.1. Configuring Hardware Name 5.7.2. Configuring MAC and IP Addresses 5.7.3. Configuring MicroC/TCP-IP Initialization 5.7.4. Configuring iPerf Server Auto-Initialization
5.7.3. Configuring MicroC/TCP-IP Initialization x
5.7.3.1. Network Task Configuration 5.7.3.2. Network Interface Configuration
5.8. MicroC/TCP-IP Simple Socket Server Concepts x
5.8.1. MicroC/OS-II Resources 5.8.2. Error Handling 5.8.3. MicroC/TCP-IP Stack Default Configuration
6. Nios® V Processor Debugging, Verifying, and Simulating x
6.1. Debugging Nios® V/c Processor 6.2. Debugging Nios® V Processor Hardware Designs 6.3. Debugging Nios® V Processor Software Designs 6.4. Debugging Tools 6.5. Additional Embedded Design Considerations 6.6. Simulating Nios® V Processor Designs
6.1. Debugging Nios® V/c Processor x
6.1.1. Pilot System with Non-pipelined Nios V/m Processor 6.1.2. printf() Debugging
6.2. Debugging Nios® V Processor Hardware Designs x
6.2.1. JTAG Server 6.2.2. System Console 6.2.3. Signal Tap Logic Analyzer 6.2.4. In-System Sources and Probes
6.2.2. System Console x
6.2.2.1. JTAG to Avalon® Host Bridge Core
6.2.3. Signal Tap Logic Analyzer x
6.2.3.1. Hardware and Software Requirements 6.2.3.2. Setting Up Signal Tap Logic Analyzer 6.2.3.3. Running the Capture Session 6.2.3.4. Analyzing Results
6.2.3.2. Setting Up Signal Tap Logic Analyzer x
6.2.3.2.1. Enabling Signal Tap Logic Analyzer 6.2.3.2.2. Adding Signals for Monitoring and Debugging 6.2.3.2.3. Specifying Trigger Conditions 6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode 6.2.3.2.5. Compiling the Design and Programming the Target Device
6.2.3.2.3. Specifying Trigger Conditions x
6.2.3.2.3.1. Basic Trigger Conditions 6.2.3.2.3.2. Power-Up Trigger Conditions 6.2.3.2.3.3. Other Trigger Conditions 6.2.3.2.3.4. No Trigger Conditions
6.2.3.3. Running the Capture Session x
6.2.3.3.1. Performing Data Capture with Ashling* RiscFree* IDE for Intel® FPGAs 6.2.3.3.2. Performing Data Capture Without Software Download
6.2.3.4. Analyzing Results x
6.2.3.4.1. Viewing Data 6.2.3.4.2. Correlating Trace Data to Software ELF 6.2.3.4.3. Saving and Converting Captured Data
6.3. Debugging Nios® V Processor Software Designs x
6.3.1. Ashling* RiscFree* IDE for Intel® FPGAs 6.3.2. OpenOCD 6.3.3. Objdump File 6.3.4. Show Make Commands
6.5. Additional Embedded Design Considerations x
6.5.1. JTAG Signal Integrity 6.5.2. Additional Memory Space for System Prototyping
6.6. Simulating Nios® V Processor Designs x
6.6.1. Prerequisites 6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer 6.6.3. Creating Nios V Processor Software 6.6.4. Generating Memory Initialization File 6.6.5. Generating System Simulation Files 6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer x
6.6.2.1. Using IP and Platform Designer Simulation Setup Scripts
6.6.3. Creating Nios V Processor Software x
6.6.3.1. Generating the Board Support Package 6.6.3.2. Generating the Application Project File 6.6.3.3. Building the Application Project
7. Nios® V Processor — Remote System Update x
7.1. Overview 7.2. Quartus® Prime Pro Edition Software and Tool Support 7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices
7.2. Quartus® Prime Pro Edition Software and Tool Support x
7.2.1. Intel® Quartus® Prime Pro Edition Software 7.2.2. Programming File Generator
7.2.1. Intel® Quartus® Prime Pro Edition Software x
7.2.1.1. Setting Max Retry Parameter 7.2.1.2. Selecting Factory Load Pin
7.2.2. Programming File Generator x
7.2.2.1. Programming File Generator File Types 7.2.2.2. Bitswap Option 7.2.2.3. Quartus® Prime Programmer 7.2.2.4. Supported QSPI Flash Devices
7.3. Nios® V Processor RSU Quick Start Guide in SDM-based Devices x
7.3.1. Individual Factory, Application, and Update Images 7.3.2. Hardware Design Flow 7.3.3. Software Design Flow 7.3.4. Individual Images Generation 7.3.5. Remote System Update Image Files Generation 7.3.6. QSPI Flash Programming 7.3.7. Operating the RSU Client API
7.3.2. Hardware Design Flow x
7.3.2.1. Create a Platform Designer System 7.3.2.2. Quartus® Prime Software Settings
7.3.3. Software Design Flow x
7.3.3.1. Generating the ZLIB libraries 7.3.3.2. Creating a Board Support Package Project 7.3.3.3. Configuring and Generating the BSP Project 7.3.3.4. Creating Multiple Application Projects 7.3.3.5. Building the Application Projects 7.3.3.6. Generating HEX Files
7.3.5. Remote System Update Image Files Generation x
7.3.5.1. Generating Initial RSU Image Using SOF file 7.3.5.2. Generating an Application Update Image 7.3.5.3. Generating a Factory Update Flash Image
7.3.6. QSPI Flash Programming x
7.3.6.1. Programming the Initial RSU Image 7.3.6.2. Programming the Update Images
7.3.7. Operating the RSU Client API x
7.3.7.1. Trigger Reconfiguration Menu with Selected Image 7.3.7.2. Updating an Application Image 7.3.7.3. Updating the Factory Image
8. Nios® V Processor — Using Custom Instruction x
8.1. Introduction 8.2. Unimplemented Instruction Example Design 8.3. Hardware Acceleration Example Design
8.2. Unimplemented Instruction Example Design x
8.2.1. Hardware and Software Requirements 8.2.2. Overview 8.2.3. Acquiring the Example Design File 8.2.4. Hardware Design Files 8.2.5. Software Design Files 8.2.6. Development Flow 8.2.7. Operating the Example Design
8.2.6. Development Flow x
8.2.6.1. Hardware Development Flow 8.2.6.2. Software Development Flow 8.2.6.3. Device Programming
8.3. Hardware Acceleration Example Design x
8.3.1. Hardware and Software Requirements 8.3.2. Overview 8.3.3. Acquiring the Example Design File 8.3.4. Hardware Design Files 8.3.5. Software Design Files 8.3.6. Development Flow 8.3.7. Operating the Example Design
8.3.6. Development Flow x
8.3.6.1. Hardware Development Flow 8.3.6.2. Software Development Flow 8.3.6.3. Device Programming
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook

4.5.3.2. Software Design Flow

This section provides the design flow to generate and build the Nios® V processor software project. To ensure a streamlined build flow, you are encouraged to create a similar directory tree in your design project. The following software design flow is based on this directory tree.

To create the software project directory tree, follow these steps:

  1. In your design project folder, create a folder called software.
  2. In the software folder, create two folders called hal_app and hal_bsp.
    Figure 46. Software Project Directory Tree

Creating the Application BSP Project

To launch the BSP Editor, follow these steps:

  1. Enter the Nios® V Command Shell.
  2. Invoke the BSP Editor with niosv-bsp-editor command.
  3. In the BSP Editor, click File > New BSP to start your BSP project.
  4. Configure the following settings:
    • SOPC Information File name: Provide the SOPCINFO file (.sopcinfo).
    • CPU name: Select Nios® V processor.
    • Operating system: Select the operating system of the Nios® V processor.
    • Version: Leave as default.
    • BSP target directory: Select the directory path of the BSP project. You can pre-set it at <Project directory>/software/hal_bsp by enabling Use default locations.
    • BSP Settings File name: Type the name of the BSP Settings File.
    • Additional Tcl scripts: Provide a BSP Tcl script by enabling Enable Additional Tcl script.
  5. Click OK.
Figure 47. Configure New BSP

Configuring the BSP Editor and Generating the BSP Project

  1. Go to Main > Settings > Advanced > hal.linker
  2. Leave all settings unchecked.
    Figure 48. Advanced.hal.linker Settings
  3. Click on the Linker Script tab in the BSP Editor.
  4. Set all regions in the Linker Section Name list to the On-Chip Memory (OCRAM) or external RAM.
    Figure 49. Linker Region Settings
  5. Click Generate BSP to generate the BSP project.

Generating the User Application Project File

  1. Navigate to the software/hal_app folder and create your application source code,
  2. Launch the Nios® V Command Shell.
  3. Execute the command below to generate the application CMakeLists.txt.
    niosv-app --app-dir=software/hal_app --bsp-dir=software/hal_bsp \
--srcs=software/hal_app/<user application>

Building the User Application Project

You can choose to build the user application project using Ashling* RiscFree* IDE for Intel® FPGAs or through the command line interface (CLI).

If you prefer using CLI, you can build the user application using the following command: 
cmake -G "Unix Makefiles" -B software/hal_app/build -S software/hal_app
make -C software/hal_app/build

The application (.elf) file is created in software/hal_app/build folder.

Generating the HEX File

You must generate a .hex file from your application .elf file, so you can create a .pof file suitable for programming the devices.

  1. Launch the Nios® V Command Shell.
  2. For Nios® V processor application boot from On-Chip Flash, use the following command line to convert the ELF to HEX for your application. This command creates the user application (onchip_flash.hex) file.
  3. Select the suitable Bootloader via GSFI in the elf2flash command.
    elf2flash
--boot <Intel Quartus Prime installation directory>/
niosv/components/bootloader/<Bootloader via GSFI>
--input software/hal_app/build/<Nios V application>.elf \
--output flash.srec --reset <reset offset + base address of On-Chip Flash> \
--base <base address of On-Chip Flash> \
--end <end address of On-Chip Flash>

    riscv32-unknown-elf-objcopy --input-target srec --output-target ihex \
flash.srec <Nios V application>.hex
  4. Recompile the hardware design if you check Initialize memory content option in On-Chip Flash IP (Method 1). This is to include the software data (.HEX) in the SOF file.
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