A newer version of this document is available. Customers should click here to go to the newest version.
1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
2.1. Creating Nios® V Processor System Design with Platform Designer
2.2. Integrating Platform Designer System into the Quartus® Prime Project
2.3. Designing a Nios® V Processor Memory System
2.4. Clocks and Resets Best Practices
2.5. Assigning a Default Agent
2.6. Assigning a UART Agent for Printing
2.7. JTAG Signals
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from On-Chip Flash (UFM)
4.6. Nios® V Processor Booting from General Purpose QSPI Flash
4.7. Nios® V Processor Booting from Configuration QSPI Flash
4.8. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.9. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.10. Summary of Nios® V Processor Vector Configuration and BSP Settings
4.11. Reducing Nios® V Processor Booting Time
6.2.3.2.1. Enabling Signal Tap Logic Analyzer
6.2.3.2.2. Adding Signals for Monitoring and Debugging
6.2.3.2.3. Specifying Trigger Conditions
6.2.3.2.4. Assigning the Acquisition Clock, Sample Depth, and Memory Type, and Buffer Acquisition Mode
6.2.3.2.5. Compiling the Design and Programming the Target Device
6.6.1. Prerequisites
6.6.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.6.3. Creating Nios V Processor Software
6.6.4. Generating Memory Initialization File
6.6.5. Generating System Simulation Files
6.6.6. Running Simulation in the QuestaSim Simulator Using Command Line
6.2.3.3.1. Performing Data Capture with Ashling* RiscFree* IDE for Intel® FPGAs
To use the Signal Tap logic analyzer with the Ashling* RiscFree* IDE for Intel® FPGAs, you must manually download a Nios® V processor software image and control the operation of the processor through the debugger. You can perform this type of capture session when you are developing and debugging a Nios® V processor software application.
Follow these steps to run a Signal Tap capture session with the Nios® V processor controlled by the Ashling* RiscFree* IDE for Intel® FPGAs:
- In the Signal Tap window, program the FPGA target device with the .sof generated:
- On the Hardware menu, select the programming cable that is connected to the FPGA development board.
- In the SOF Manager field, click browse.
- In the Select Programming File dialog box, select the .sof generated.
- Click Open. The Program Device button is now available.
- Click the Program Device button to download the .sof to the FPGA.
- In the Signal Tap window, in the Instance Manager pane, click the Run Analysis button to start the logic analyzer capture session.
- In the Ashling* RiscFree* IDE for Intel® FPGAs, right-click the name of the software project you want to run on the Nios® V processor and click Debug As > Debug Configuration > Ashling RISC-V Hardware Debugging.
- Set the necessary debug configuration. This action starts the debugger, downloads the .elf into system memory, and halts the processor on the entry point to main().
- On the Debug tab, click the Resume button to start the Nios® V processor execution
The Signal Tap logic analyzer continues running until the trigger condition specified is reached. While the Signal Tap logic analyzer is running, you can use the Ashling* RiscFree* IDE for Intel® FPGAs debugger at the same time safely (for example, you can set breakpoints and stop the processor).
To change the startup breakpoint, follow these steps in the Ashling* RiscFree* IDE for Intel® FPGAs:
- On the Run menu, click Debug Configurations.
- The Debug Configurations window appears.
- In the Debug Configurations window, click the Startup tab.
- Specify a new startup breakpoint at Set breakpoint at.
- Click Apply.
Alternatively, instead of using the Debug As option, you can use the Run As option. Using the Run As option causes the Ashling* RiscFree* IDE for Intel® FPGAs to download and run the software image from system memory without starting the debugger feature.