F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

Download PDF
ID 720989
Date 2/23/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide 2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters 6. Interface Signals 7. Configuration Registers A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Device Speed Grade Support 2.5. Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Specifying the IP Core Parameters and Options 3.4. Generated File Structure 3.5. Simulating Intel® FPGA IP Cores 3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 3.7. Integrating Your IP Core in Your Design
3.2. Installing and Licensing Intel® FPGA IP Cores x
3.2.1. Intel® FPGA IP Evaluation Mode
3.7. Integrating Your IP Core in Your Design x
3.7.1. Adding the F-tile Reference and System PLL IP
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed 4.4. IEEE 802.3 Clause 37 Auto-Negotiation 4.5. USXGMII
4.1. Clocking and Reset Sequence x
4.1.1. Clocking 4.1.2. Reset
6. Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. Serial Interface Signals 6.4. Avalon® Memory-Mapped Interface Signals 6.5. XGMII Signals 6.6. Transceiver Status and Transceiver Clock Status Signals 6.7. Reconfiguration Signals 6.8. Operating Speed and Status Signals
7. Configuration Registers x
7.1. Register Map 7.2. PHY Registers
1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

6.1. Clock Signals

Table 15.  Clock Signals
Signal Name Direction Width Description
csr_clk Input 1 Clock for the Avalon® memory-mapped control and status interface. Intel recommends 100 to 156.25 MHz for this clock.
xgmii_tx_coreclkin Input 1 TX clock for XGMII logic before phase compensation FIFO. Provides a 312.5 MHz timing reference for the 10M/100M/1G/2.5G/5G/10G (USXGMII) mode.
xgmii_rx_coreclkin Input 1 RX clock for XGMII logic after rate matcher. Provides a 312.5 MHz timing reference for the 10M/100M/1G/2.5G/5G/10G (USXGMII) mode.
tx_pma_clk Input 1 TX clock of soft PCS (interface with F-tile Ethernet Hard IP). Provides a 322.265625 MHz timing reference for the 10M/100M/1G/2.5G/5G/10G (USXGMII) mode.

Tie this signal to o_clk_pll.

rx_pma_clk Input 1 RX clock of soft PCS (interface with F-tile Ethernet Hard IP). Provides a 322.265625 MHz timing reference for the 10M/100M/1G/2.5G/5G/10G (USXGMII) mode.

Tie this signal to o_clk_pll.

o_clk_pll Output 1

322.265625 MHz clock derived from the F-Tile System PLL associated with this Ethernet Port. The frequency is the system PLL frequency divided by 2

Source i_tx_clk_clk and i_rx_clk_clk from o_clk_pll of this or another IP on the same system clock, or a parts per million (ppm)-matched clock of the same frequency. Do not use o_clk_pll until o_sys_pll_locked is asserted.

Refer to Figure 8 for the details on clock connectivity.

i_tx_clk_clk Input 1

322.265625 MHz TX datapath clock.

This signal drives the active TX Interface for the port.

Source this signal from o_clk_pll.

i_rx_clk_clk Input 1

322.265625 MHz RX datapath clock.

This signal drives the active RX Interface for the port.

Source this signal from o_clk_pll.

i_reconfig_clk Input 1 Reconfiguration clock for Avalon® memory-mapped interfaces (The interface uses this clock to access Ethernet reconfiguration and transceiver reconfiguration of the F-tile Ethernet Hard IP). Intel recommends 100 to 156.25 MHz for this clock.
i_clk_ref Input 1 156.25/312.5/322.2656 MHz transceiver reference clock (from F-tile Reference and System PLL Clocks IP). This port connects to a virtual “Link” net that carries no signal.
Note: The i_clk_ref is a virtual signal. In simulation, the signal displays as 0.
i_clk_sys Input 1 644.53125 MHz Ethernet system clock (from F-tile Reference and System PLL Clocks IP).
Note: The i_clk_sys is a virtual signal. In simulation, the signal displays as 0.
i_clk_pll Input 1

This clock drives the internal datapath clock for the port for the case "Enable IEEE 1588 PTP" (Not available in the current Quartus release). Tie this signal to ground.

Level Two Title