F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

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ID 720989
Date 2/23/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide 2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters 6. Interface Signals 7. Configuration Registers A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Device Speed Grade Support 2.5. Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Specifying the IP Core Parameters and Options 3.4. Generated File Structure 3.5. Simulating Intel® FPGA IP Cores 3.6. Upgrading the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 3.7. Integrating Your IP Core in Your Design
3.2. Installing and Licensing Intel® FPGA IP Cores x
3.2.1. Intel® FPGA IP Evaluation Mode
3.7. Integrating Your IP Core in Your Design x
3.7.1. Adding the F-tile Reference and System PLL IP
4. Functional Description x
4.1. Clocking and Reset Sequence 4.2. Timing Constraints 4.3. Switching Operation Speed 4.4. IEEE 802.3 Clause 37 Auto-Negotiation 4.5. USXGMII
4.1. Clocking and Reset Sequence x
4.1.1. Clocking 4.1.2. Reset
6. Interface Signals x
6.1. Clock Signals 6.2. Reset Signals 6.3. Serial Interface Signals 6.4. Avalon® Memory-Mapped Interface Signals 6.5. XGMII Signals 6.6. Transceiver Status and Transceiver Clock Status Signals 6.7. Reconfiguration Signals 6.8. Operating Speed and Status Signals
7. Configuration Registers x
7.1. Register Map 7.2. PHY Registers
1. About the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
A. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP User Guide

4.3. Switching Operation Speed

Table 11.  Operating Speed Switching Methodology
PHY Configuration Speed Switch Methodology
10M/100M/1G/2.5G/5G/10G (USXGMII) Auto-speed switching via USXGMII Auto-Negotiation or manual speed switching via CSR available inside the PHY.
Table 12.  Supported Operating Speed
PHY Configuration Features 10M 100M 1G 2.5G 5G 10G
10M/100M/1G/2.5G/5G/10G (USXGMII) Protocol 10GBASE-R

1000x data replication

 10GBASE-R

100x data replication

 10GBASE-R

10x data replication

 10GBASE-R

4x data replication

 10GBASE-R

2x data replication

 10GBASE-R

No data replication
Transceiver Data Rate1 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps 10.3125 Gbps
MAC Interface 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz 32-bit XGMII @ 312.5 MHz
1 With oversampling for lower data rates.
Level Two Title