F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

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ID 720987
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 4. Interface Signals Description 5. Configuration Registers Description 6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design 2.3. Compiling and Simulating the Design 2.4. Compiling and Testing the Design in Hardware 2.5. Signal Tap Debugging
2.2. Generating the Design x
2.2.1. Procedure 2.2.2. Design Example Parameters
2.3. Compiling and Simulating the Design x
2.3.1. Procedure 2.3.2. Testbench
2.4. Compiling and Testing the Design in Hardware x
2.4.1. Procedure 2.4.2. Hardware Setup
2.5. Signal Tap Debugging x
2.5.1. Signal Tap Debug Signals
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.3.3. Reset Scheme x
3.3.3.1. Reset Sequence
3.3.3.1. Reset Sequence x
3.3.3.1.1. Run-time Reset Sequence—TX 3.3.3.1.2. Run-time Reset Sequence—RX 3.3.3.1.3. Run-time Reset Sequence—TX + RX
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 3.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Procedure 3.5.2. Design Constraints
4. Interface Signals Description x
4.1. Clock and Reset Interface Signals 4.2. Avalon® Memory-Mapped Interface Signals 4.3. Avalon® Streaming Interface Signals 4.4. PHY Interface Signals 4.5. Status Interface 4.6. IEEE 1588v2 Timestamp Interface Signals 4.7. Packet Classifier Interface Signals 4.8. TOD Interface Signals
5. Configuration Registers Description x
5.1. Register Access Definition 5.2. Low Latency Ethernet 10G MAC 5.3. PHY 5.4. TOD
5.3. PHY x
5.3.1. 1G/2.5G/5G/10G Multirate PHY
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

2.5.1. Signal Tap Debug Signals

Table 6.  List of Debug Signals for Signal Tap
Signal Description
avalon_st_tx_valid Assert this signal to indicate that the avalon_st_tx_data signal and other signals on this interface are valid.
avalon_st_tx_ready When asserted, indicates that the MAC IP is ready to accept data. The reset value of this signal is nondeterministic.
avalon_st_tx_startofpacket Assert this signal to indicate the beginning of the TX data.
avalon_st_tx_endofpacket Assert this signal to indicate the end of the TX data.
avalon_st_tx_data[63:0] TX data from the client.
avalon_st_tx_empty[2:0] Use this signal to specify the number of empty bytes in the cycle that contain the end of the TX data.
avalon_st_tx_error Assert this signal to indicate that the current TX packet contains errors.
avalon_st_rx_valid Assert this signal to indicate that the avalon_st_rx_data signal and other signals on this interface are valid.
avalon_st_rx_ready Assert this signal when the client is ready to accept data.
avalon_st_rx_startofpacket When asserted, indicates the beginning of the RX data.
avalon_st_rx_endofpacket When asserted, indicates the end of the RX data.
avalon_st_rx_data[63:0] RX data to the client.
avalon_st_rx_empty[2:0] Contains the number of empty bytes during the cycle that contain the end of the RX data.
avalon_st_rx_error[5:0] When set to 1, the respective bits indicate an error type:
  • Bit 0—PHY error.
    • The data on xgmii_rx_data contains a control error character (FE).
  • Bit 1—CRC error. The computed CRC value does not match the CRC received.
  • Bit 2—Undersized frame. The receive frame length is less than 64 bytes.
  • Bit 3—Oversized frame. The receive frame length is more than MAX_FRAME_SIZE.
  • Bit 4—Payload length error. The actual frame payload length is different from the value in the length/type field.
  • Bit 5—Overflow error. The receive FIFO buffer is full while it is still receiving data from the MAC IP.
avalon_st_txstatus_valid

When asserted, this signal qualifies the avalon_st_txstatus_data and avalon_st_txstatus_error signals.

avalon_st_rx_valid When asserted, indicates that the avalon_st_rx_data signal and other signals on this interface are valid.
avalon_st_txstatus_data[39:0]

Contains information about the TX frame.

  • Bits 0 to 15: Payload length.
  • Bits 16 to 31: Packet length.
  • Bit 32: When set to 1, indicates a stacked VLAN frame.
  • Bit 33: When set to 1, indicates a VLAN frame.
  • Bit 34: When set to 1, indicates a control frame.
  • Bit 35: When set to 1, indicates a pause frame.
  • Bit 36: When set to 1, indicates a broadcast frame.
  • Bit 37: When set to 1, indicates a multicast frame.
  • Bit 38: When set to 1, indicates a unicast frame.
  • Bit 39: When set to 1, indicates a PFC frame.
avalon_st_txstatus_error[6:0]

When set to 1, the respective bit indicates the following error type in the TX frame:

  • Bit 0: Undersized frame.
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error.
  • Bit 3: Unused.
  • Bit 4: Underflow.
  • Bit 5: Client error.
  • Bit 6: Unused.
avalon_st_rxstatus_valid When asserted, this signal qualifies the avalon_st_rxstatus_data and avalon_st_rxstatus_error signals.

The MAC IP asserts this signal in the same clock cycle the avalon_st_rx_ endofpacket signal is asserted.

avalon_st_rxstatus_data[39:0]

Contains information about the RX frame.

  • Bits 0 to 15: Payload length.
  • Bits 16 to 31: Packet length.
  • Bit 32: When set to 1, indicates a stacked VLAN frame.
  • Bit 33: When set to 1, indicates a VLAN frame.
  • Bit 34: When set to 1, indicates a control frame.
  • Bit 35: When set to 1, indicates a pause frame.
  • Bit 36: When set to 1, indicates a broadcast frame.
  • Bit 37: When set to 1, indicates a multicast frame.
  • Bit 38: When set to 1, indicates a unicast frame.
  • Bit 39: When set to 1, indicates a PFC frame.
avalon_st_rxstatus_error[6:0]

When set to 1, the respective bit indicates the following error type in the RX frame.

  • Bit 0: Undersized frame.
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error.
  • Bit 3: Unused.
  • Bit 4: Underflow.
  • Bit 5: Client error.
  • Bit 6: Unused.

The error status is invalid when an overflow occurs.
led_an Asserted when auto-negotiation is completed.
o_rx_pcs_ready Active-high asynchronous status signal for the RX datapath. Asserts when the RX datapath is ready to receive data. Deasserts when i_rx_rst_n/i_rst_n signal asserts.
o_cdr_lock This signal indicates that the recovered clocks are locked to data.
channel_tx_ready Asserted when the channel is ready for data transmission.
channel_rx_ready Asserted when the channel is ready for data transmission.
rx_block_lock Asserted when the link synchronization is successful.
frame_dropped Frame dropped signal from the RX block.
overflow_reg Overflow bit from the RX block.
eop_extended Extended end of packet signal from the RX block.
rx_rs2fctl_frm_error Frame error bit signal in the RX block.
rx_rs2fctl_frm_data [31:0] Frame input data signal .
rx_rs2fctl_frm_sop Start of packet input signal at RX block frame.
rx_rs2fctl_frm_eop End of packet input signal at RX block frame.
rx_rs2fctl_frm_valid Input valid signal at RX block frame.
rx_rs2fctl_frm_empty [1:0] Input empty signal at RX block frame.
rx_fltrpcrem2pa_frm_data [31:0] Frame output data.
rx_fltrpcrem2pa_frm_sop Start of packet output signal at RX block frame.
rx_fltrpcrem2pa_frm_eop End of packet output signal at RX block frame.
rx_fltrpcrem2pa_frm_valid Output valid signal at RX block frame.
rx_fltrpcrem2pa_frm_empty [1:0] Output empty signal at RX block frame.
rx_fltrpcrem2pa_frm_error Frame error bit in the RX block.
Note: The signal tap debug signals are targetted for channel 0 and are used in channel 0 tests.
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