F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

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ID 720987
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 4. Interface Signals Description 5. Configuration Registers Description 6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design 2.3. Compiling and Simulating the Design 2.4. Compiling and Testing the Design in Hardware 2.5. Signal Tap Debugging
2.2. Generating the Design x
2.2.1. Procedure 2.2.2. Design Example Parameters
2.3. Compiling and Simulating the Design x
2.3.1. Procedure 2.3.2. Testbench
2.4. Compiling and Testing the Design in Hardware x
2.4.1. Procedure 2.4.2. Hardware Setup
2.5. Signal Tap Debugging x
2.5.1. Signal Tap Debug Signals
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.3.3. Reset Scheme x
3.3.3.1. Reset Sequence
3.3.3.1. Reset Sequence x
3.3.3.1.1. Run-time Reset Sequence—TX 3.3.3.1.2. Run-time Reset Sequence—RX 3.3.3.1.3. Run-time Reset Sequence—TX + RX
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 3.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Procedure 3.5.2. Design Constraints
4. Interface Signals Description x
4.1. Clock and Reset Interface Signals 4.2. Avalon® Memory-Mapped Interface Signals 4.3. Avalon® Streaming Interface Signals 4.4. PHY Interface Signals 4.5. Status Interface 4.6. IEEE 1588v2 Timestamp Interface Signals 4.7. Packet Classifier Interface Signals 4.8. TOD Interface Signals
5. Configuration Registers Description x
5.1. Register Access Definition 5.2. Low Latency Ethernet 10G MAC 5.3. PHY 5.4. TOD
5.3. PHY x
5.3.1. 1G/2.5G/5G/10G Multirate PHY
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.07.08 24.2 22.2.0
  • Removed a note in the Procedure topic.
  • Added Signal Tap Debugging and Signal Tap Debugging Signals topics.
  • Added Reset Sequence topic.
  • Added Run-time Reset Sequence—TX topic.
  • Added Run-time Reset Sequence—RX topic.
  • Added Run-time Reset Sequence—TX + RX topic.
  • Updated description for i_reconfig_reset, i_tx_rst_n, and i_rx_rst_n signals in the Clock and Reset Interface Signals table.
  • Added i_rst_n signal in the Clock and Reset Interface Signals table.
2023.11.29 23.3 22.0.3
  • Updated the OPN number for Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit.
  • Updated Procedure for Compiling and Simulating the Design topic.
  • Added Design Constraints topic.
  • Updated product family name to "Intel Agilex® 7".
2022.12.20 22.4 22.0.0
  • Updated Procedure topic with additional simulators.
  • Added multi-channel designs support:
    • Updated Block Diagram of the Testbench in the Testbench topic.
    • Updated Block Diagram of the Hardware Setup figure in the Hardware Setup topic.
    • Updated the Features topic to add support for dual Ethernet channel.
    • Updated the Block Diagram—10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example Without IEEE 1588v2 Feature and Block Diagram—10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With IEEE 1588v2 Feature figure in Functional Description topic.
    • Updated Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example Without IEEE 1588v2 Feature and Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With IEEE 1588v2 Feature figure in Clocking Scheme topic.
    • Updated figure title Reset Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With and Without IEEE 1588v2 Feature (Reset is common for all instance)
    • Updated Command Parameters table.
    • Updated Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with the IEEE 1588v2 Feature figure.
2022.06.21 22.2 20.1.0 Added PTP support for 10M/100M/1G/2.5G/5G/10G USXGMII variant
  • Updated Directory Structure for the Design Example diagram.
  • Updated the Design Example Parameters topic.
  • Updated the Compiling and Simulating the Design topic.
  • Updated Features topic.
  • Added a new Figure: Block Diagram—10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With IEEE 1588v2 Feature.
  • Updated the Design Components topic.
  • Added a new Figure: Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588v2 Feature
  • Updated Simulation topic.
  • Updated Hardware Testing topic.
  • Updated Test Procedure topic.
  • Added a new Figure: Interface Signals of the Design Example with PTP.
  • Added IEEE 1588v2 Timestamp Interface Signals topic.
  • Added TOD topic.
2022.04.01 21.4.1 20.0.0 Initial release.
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