F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

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ID 720987
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 4. Interface Signals Description 5. Configuration Registers Description 6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design 2.3. Compiling and Simulating the Design 2.4. Compiling and Testing the Design in Hardware 2.5. Signal Tap Debugging
2.2. Generating the Design x
2.2.1. Procedure 2.2.2. Design Example Parameters
2.3. Compiling and Simulating the Design x
2.3.1. Procedure 2.3.2. Testbench
2.4. Compiling and Testing the Design in Hardware x
2.4.1. Procedure 2.4.2. Hardware Setup
2.5. Signal Tap Debugging x
2.5.1. Signal Tap Debug Signals
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.3.3. Reset Scheme x
3.3.3.1. Reset Sequence
3.3.3.1. Reset Sequence x
3.3.3.1.1. Run-time Reset Sequence—TX 3.3.3.1.2. Run-time Reset Sequence—RX 3.3.3.1.3. Run-time Reset Sequence—TX + RX
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 3.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Procedure 3.5.2. Design Constraints
4. Interface Signals Description x
4.1. Clock and Reset Interface Signals 4.2. Avalon® Memory-Mapped Interface Signals 4.3. Avalon® Streaming Interface Signals 4.4. PHY Interface Signals 4.5. Status Interface 4.6. IEEE 1588v2 Timestamp Interface Signals 4.7. Packet Classifier Interface Signals 4.8. TOD Interface Signals
5. Configuration Registers Description x
5.1. Register Access Definition 5.2. Low Latency Ethernet 10G MAC 5.3. PHY 5.4. TOD
5.3. PHY x
5.3.1. 1G/2.5G/5G/10G Multirate PHY
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

4.7. Packet Classifier Interface Signals

Table 17.  Packet Classifier Interface Signals
Signal Direction Width Description
tx_egress_timestamp_request_ in_valid[] In [NUM_CHANNELS] Assert this signal to request timestamping for the TX frame. This signal must be asserted in the same clock cycle avalon_st_tx_startofpacket is asserted.
tx_egress_timestamp_request_ in_fingerprint[][] In [NUM_CHANNELS][TSTAMP_ FP_WIDTH] Use this bus to specify the fingerprint that validates the timestamp for the incoming packet.
clock_operation_mode_mode[][] In [NUM_CHANNELS][2] Use this signal to specify the clock mode.
  • 00: Ordinary clock
  • 01: Boundary clock
  • 10: End to end transparent clock
  • 11: Peer to peer transparent clock
pkt_with_crc_mode[] In [NUM_CHANNELS] Use this signal to specify whether or not a packet contains CRC.
  • 0: Packet contains CRC
  • 1: Packet does not contain CRC
tx_ingress_timestamp_valid[] In [NUM_CHANNELS] Indicates whether or not the residence time can be updated.
  • 0: Prevents update for residence time
  • 1: Allows update for residence time based on decoded results

When this signal is deasserted, the tx_etstamp_ins_ctrl_out_residence_ti me_update signal also gets deasserted.

tx_ingress_timestamp_96b_ data[][] In [NUM_CHANNELS][96] 96-bit format of ingress timestamp that holds the data so that the output can align with the start of an incoming packet.
tx_ingress_timestamp_64b_ data[][] In [NUM_CHANNELS][64] 64-bit format of ingress timestamp that holds the data so that the output can align with the start of an incoming packet.
tx_ingress_timestamp_format[] In [NUM_CHANNELS] The format of the timestamp for calculating the residence time.
  • 0: 96 bits
  • 1: 64 bits

This signal must be aligned to the start of an incoming packet.
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