F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 5/01/2024
Public
Document Table of Contents

1.5. Resource Utilization

Table 4.  Resource Utilization for Agilex™ 7 DevicesThese results were obtained using the Quartus® Prime software version 22.1 with the following conditions:
  • All reconfiguration groups have client interface set to MAC segmented.
  • The resource utilization is specific to FGT reconfiguration groups.
  • The resource utilization excludes the soft logic utilization for the *_Tiles file, generated by Quartus® Prime software after the support logic generation phase.
    • The *_Tiles file uses approx. 5,000 combinatorial ALUTs, 6,000 logic registers, and 164,000 bits of block memory bits.
Reconfiguration Group

(with selected MAC mode)

Combinatorial ALUTs Logic Registers Block Memory Bits
25GE-1 1,407 2,420 0
50GE-1 1,851 4,167 0
100GE-4 6,551 14,381 0
100GE-4 (including 40GE) 7,489 15,718 0
100GE-2 4,116 10,490 0
400GE-8 10,930 28,795 0
200GE-4 8,144 21,347 0