F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 5/01/2024
Public
Document Table of Contents

2.14. Avalon® Memory-Mapped Reconfiguration Interfaces

The F-Tile Ethernet Multirate IP core supports these Avalon® memory-mapped interfaces:
  • Ethernet reconfiguration Avalon® memory-mapped interface access the hard and soft IP CSRs. Each port instantiates one interface.
  • Transceiver reconfiguration Avalon® memory-mapped interface accesses the transceiver registers. Each transceiver lane instantiates one interface.
The table depicts the interface for different numbers of ports.
Table 65.  Signals of the Ethernet Reconfiguration Avalon® Memory-Mapped Interface For signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Number of Ports Signal Name
1

Port 0:

i_p0_reconfig_eth_addr[13:0]

i_p0_reconfig_eth_read

i_p0_reconfig_eth_write

i_p0_reconfig_eth_byteenable[3:0]

o_p0_reconfig_eth_readdata[31:0]

o_p0_reconfig_eth_readdata_valid

i_p0_reconfig_eth_writedata[31:0]

o_p0_reconfig_eth_waitrequest

2

Port 0:

i_p0_reconfig_eth_addr[13:0]

i_p0_reconfig_eth_read

i_p0_reconfig_eth_write

i_p0_reconfig_eth_byteenable[3:0]

o_p0_reconfig_eth_readdata[31:0]

o_p0_reconfig_eth_readdata_valid

i_p0_reconfig_eth_writedata[31:0]

o_p0_reconfig_eth_waitrequest

Port 1:

i_p1_reconfig_eth_addr[13:0]

i_p1_reconfig_eth_read

i_p1_reconfig_eth_write

i_p1_reconfig_eth_byteenable[3:0]

o_p1_reconfig_eth_readdata[31:0]

o_p1_reconfig_eth_readdata_valid

i_p1_reconfig_eth_writedata[31:0]

o_p1_reconfig_eth_waitrequest

4

Port 0:

i_p0_reconfig_eth_addr[13:0]

i_p0_reconfig_eth_read

i_p0_reconfig_eth_write

i_p0_reconfig_eth_byteenable[3:0]

o_p0_reconfig_eth_readdata[31:0]

o_p0_reconfig_eth_readdata_valid

i_p0_reconfig_eth_writedata[31:0]

o_p0_reconfig_eth_waitrequest

Port 1:

i_p1_reconfig_eth_addr[13:0]

i_p1_reconfig_eth_read

i_p1_reconfig_eth_write

i_p1_reconfig_eth_byteenable[3:0]

o_p1_reconfig_eth_readdata[31:0]

o_p1_reconfig_eth_readdata_valid

i_p1_reconfig_eth_writedata[31:0]

o_p1_reconfig_eth_waitrequest

Port 2:

i_p2_reconfig_eth_addr[13:0]

i_p2_reconfig_eth_read

i_p2_reconfig_eth_write

i_p2_reconfig_eth_byteenable[3:0]

o_p2_reconfig_eth_readdata[31:0]

o_p2_reconfig_eth_readdata_valid

i_p2_reconfig_eth_writedata[31:0]

o_p2_reconfig_eth_waitrequest

Port 3:

i_p3_reconfig_eth_addr[13:0]

i_p3_reconfig_eth_read

i_p3_reconfig_eth_write

i_p3_reconfig_eth_byteenable[3:0]

o_p3_reconfig_eth_readdata[31:0]

o_p3_reconfig_eth_readdata_valid

i_p3_reconfig_eth_writedata[31:0]

o_p3_reconfig_eth_waitrequest

For information about the transceiver reconfiguration Avalon® memory-mapped interface, refer to the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.