F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 5/01/2024
Public
Document Table of Contents

2.16.6. PTP Status Interface

A separate PTP status interface is available for each supported port within a reconfiguration group. The below table shows the interface details for different number of ports.

Table 72.  Signals of the PTP Status InterfaceFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Maximum Number of Ports Applicable Reconfiguration Groups Signal Name
1

FGT:

25GE-1 Reconfigurable

50GE-1 Reconfigurable

FHT:

50GE-1 Reconfigurable

100GE-1 Reconfigurable

Port 0:

o_p0_tx_ptp_offset_data_valid

o_p0_rx_ptp_offset_data_valid

o_p0_tx_ptp_ready

o_p0_rx_ptp_ready

2

FGT:

100GE-2 Reconfigurable

FHT:

100GE-2 Reconfigurable

200GE-2 Reconfigurable

Port 0:

o_p0_tx_ptp_offset_data_valid

o_p0_rx_ptp_offset_data_valid

o_p0_tx_ptp_ready

o_p0_rx_ptp_ready

4

FGT:

100GE-4 Reconfigurable

400GE-8 Reconfigurable

200GE-4 Reconfigurable

FHT:

100GE-4 Reconfigurable

400GE-4 Reconfigurable

200GE-4 Reconfigurable

Port 0:

o_p0_tx_ptp_offset_data_valid

o_p0_rx_ptp_offset_data_valid

o_p0_tx_ptp_ready

o_p0_rx_ptp_ready

Port 1:

o_p1_tx_ptp_offset_data_valid

o_p1_rx_ptp_offset_data_valid

o_p1_tx_ptp_ready

o_p1_rx_ptp_ready

Port 2:

o_p2_tx_ptp_offset_data_valid

o_p2_rx_ptp_offset_data_valid

o_p2_tx_ptp_ready

o_p2_rx_ptp_ready

Port 3:

o_p3_tx_ptp_offset_data_valid

o_p3_rx_ptp_offset_data_valid

o_p3_tx_ptp_ready

o_p3_rx_ptp_ready