F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 5/01/2024
Public
Document Table of Contents

2.9. Fractured MII PCS-Only Interface for FHT Transceivers

This section describes the fractured interface signals when you select the MII PCS-only client interface in the IP parameter editor.

The datapath interface consists of a fractured interface where the same set of signals is re-used for a single or multiple port datapath connections.

The following tables displays the ports details and the supported variants for each of the reconfiguration groups. The mode selection refers to the Ethernet mode parameter in the F-Tile Ethernet Multirate IP core Profile # IP Configuration tab.

Table 43.  Signals of the Fractured MII PCS-only Interface for 50GE-1 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[127:0]

i_tx_mii_valid

i_tx_mii_c[15:0]

i_tx_mii_am

o_tx_mii_ready

o_rx_mii_d[127:0]

o_rx_mii_valid

o_rx_mii_am_valid

o_rx_mii_c[15:0]

1x 25GE-1/

Port 0:

i_tx_mii_d[63:0]

i_tx_mii_valid

i_tx_mii_c[7:0]

i_tx_mii_am

o_tx_mii_ready

Port 0:

o_rx_mii_d[63:0]

o_rx_mii_valid

o_rx_mii_am_valid

o_rx_mii_c[7:0]

1x50GE-1

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid

i_tx_mii_c[15:0]

i_tx_mii_am

o_tx_mii_ready

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid

o_rx_mii_am_valid

o_rx_mii_c[7:0]

Table 44.  Signals of the Fractured MII PCS-only Interface for 100GE-4 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[255:0]

i_tx_mii_valid[3:0]

i_tx_mii_c[31:0]

i_tx_mii_am[3:0]

o_tx_mii_ready[3:0]

o_rx_mii_d[255:0]

o_rx_mii_valid[3:0]

o_rx_mii_c[31:0]

o_rx_mii_am_valid[3:0]

4x 25GE-1

Port 0:

i_tx_mii_d[63:0]

i_tx_mii_valid[0]

i_tx_mii_c[7:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[127:64]

i_tx_mii_valid[1]

i_tx_mii_c[15:8]

i_tx_mii_am[1]

o_tx_mii_ready[1]

Port 2:

i_tx_mii_d[191:128]

i_tx_mii_valid[2]

i_tx_mii_c[23:16]

i_tx_mii_am[2]

o_tx_mii_ready[2]

Port 3:

i_tx_mii_d[255:192]

i_tx_mii_valid[3]

i_tx_mii_c[31:24]

i_tx_mii_am[3]

o_tx_mii_ready[3]

Port 0:

o_rx_mii_d[63:0]

o_rx_mii_valid[0]

o_rx_mii_c[7:0]

o_rx_mii_am_valid[0]

Port 1:

o_rx_mii_d[127:64]

o_rx_mii_c[15:8]

o_rx_mii_valid[1]

o_rx_mii_am_valid[1]

Port 2:

o_rx_mii_d[191:128]

o_rx_mii_valid[2]

o_rx_mii_c[23:16]

o_rx_mii_am_valid[2]

Port 3:

o_rx_mii_d[255:192]

o_rx_mii_valid[3]

o_rx_mii_c[31:24]

o_rx_mii_am_valid[3]

2x 50GE-2/

2x50GE-1

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid

i_tx_mii_c[15:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 2:

i_tx_mii_d[255:128]

i_tx_mii_valid[2]

i_tx_mii_c[31:16]

i_tx_mii_am[2]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_c[15:0]

o_rx_mii_am_valid[0]

Port 2:

o_rx_mii_d[255:128]

o_rx_mii_valid[2]

o_rx_mii_c[31:16]

o_rx_mii_am_valid[2]

1x 100GE-4/

1x 100GE-2/

1x 100GE-1

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_c[31:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_c[31:0]

o_rx_mii_am_valid[0]

Table 45.  Signals of the Fractured MII PCS-only Interface for 100GE-2 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[255:0]

i_tx_mii_valid[1:0]

i_tx_mii_c[31:0]

i_tx_mii_am[1:0]

o_tx_mii_ready[1:0]

o_rx_mii_d[255:0]

o_rx_mii_valid[1:0]

o_rx_mii_am_valid[1:0]

o_rx_mii_c[31:0]

1x100GE-2/

1x 100GE-1

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_c[31:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_c[31:0]

o_rx_mii_am_valid[0]

2x 50GE-1

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid[0]

i_tx_mii_c[15:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[255:128]

i_tx_mii_valid[1]

i_tx_mii_c[31:16]

i_tx_mii_am[1]

o_tx_mii_ready[1]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_c[15:0]

o_rx_mii_am_valid[0]

Port 1:

o_rx_mii_d[255:128]

o_rx_mii_valid[1]

o_rx_mii_c[31:16]

o_rx_mii_am_valid[1]

2x 25GE-1

Port 0:

i_tx_mii_d[63:0]

i_tx_mii_valid[0]

i_tx_mii_c[7:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[191:128]

i_tx_mii_valid[1]

i_tx_mii_c[23:16]

i_tx_mii_am[1]

o_tx_mii_ready[1]

Port 0:

o_rx_mii_d[63:0]

o_rx_mii_valid[0]

o_rx_mii_am_valid[0]

o_rx_mii_c[7:0]

Port 1:

o_rx_mii_d[191:128]

o_rx_mii_valid[1]

o_rx_mii_c[23:16]

o_rx_mii_am_valid[1]

1x 50GE-2

i_tx_mii_d[127:0]

i_tx_mii_valid[0]

i_tx_mii_c[15:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_c[15:0]

o_rx_mii_am_valid[0]

Table 46.  Signals of the Fractured MII PCS-only Interface for 100GE-1 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[255:0]

i_tx_mii_valid

i_tx_mii_c[31:0]

i_tx_mii_am

o_tx_mii_ready

o_rx_mii_d[255:0]

o_rx_mii_valid

o_rx_mii_c[31:0]

o_rx_mii_am_valid

1x 100GE-1

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid

i_tx_mii_c[31:0]

i_tx_mii_am

o_tx_mii_ready

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid

o_rx_mii_c[31:0]

o_rx_mii_am_valid

1x 50GE-1

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid

i_tx_mii_am

i_tx_mii_c[15:0]

o_tx_mii_ready

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid

o_rx_mii_c[15:0]

o_rx_mii_am_valid

1x 25GE-1

Port 0:

i_tx_mii_d[63:0]

i_tx_mii_valid

i_tx_mii_c[7:0]

i_tx_mii_am

o_tx_mii_ready

Port 0:

o_rx_mii_d[63:0]

o_rx_mii_valid

o_rx_mii_c[7:0]

o_rx_mii_am_valid

Table 47.  Signals of the Fractured MII PCS-only Interface for 400GE-4 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[1023:0]

i_tx_mii_valid[3:0]

i_tx_mii_c[127:0]

i_tx_mii_am[3:0]

o_tx_mii_ready[3:0]

o_rx_mii_d[1023:0]

o_rx_mii_valid[3:0]

o_rx_mii_c[127:0]

o_rx_mii_am_valid[3:0]

1x 400GE-4

Port 0:

i_tx_mii_d[1023:0]

i_tx_mii_valid[0]

i_tx_mii_c[127:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[1023:0]

o_rx_mii_valid[0]

o_rx_mii_c[127:0]

o_rx_mii_am_valid[0]

1x 200GE-4

Port 0:

i_tx_mii_d[511:0]

i_tx_mii_valid[0]

i_tx_mii_c[63:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[511:0]

o_rx_mii_valid[0]

o_rx_mii_c[63:0]

o_rx_mii_am_valid[0]

2x 200GE-2

Port 0:

i_tx_mii_d[511:0]

i_tx_mii_valid[0]

i_tx_mii_c[63:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 2:

i_tx_mii_d[1023:512]

i_tx_mii_valid[2]

i_tx_mii_c[127:64]

i_tx_mii_am[2]

o_tx_mii_ready[2]

Port 0:

o_rx_mii_d[511:0]

o_rx_mii_valid[0]

o_rx_mii_c[63:0]

o_rx_mii_am_valid[0]

Port 2:

o_rx_mii_d[1023:512]

o_rx_mii_valid[2]

o_rx_mii_c[127:64]

o_rx_mii_am_valid[2]

2x100GE-2

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_c[31:0]

i_tx_mii_am[0]

o_tx_mii_ready[0

Port 2:

i_tx_mii_d[767:512]

i_tx_mii_valid[2]

i_tx_mii_c[95:64]

i_tx_mii_am[2]

o_tx_mii_ready[2]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_c[31:0]

o_rx_mii_am_valid[3:0]

Port 2:

o_rx_mii_d[767:512]

o_rx_mii_valid[2]

o_rx_mii_c[95:64]

o_rx_mii_am_valid[2]

4x100GE-1 Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_c[31:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[511:256]

i_tx_mii_valid[1]

i_tx_mii_c[63:32]

i_tx_mii_am[1]

o_tx_mii_ready[1]

Port 2:

i_tx_mii_d[767:512]

i_tx_mii_valid[2]

i_tx_mii_c[95:64]

i_tx_mii_am[2]

o_tx_mii_ready[2]

Port 3:

i_tx_mii_d[1023:768]

i_tx_mii_valid[3]

i_tx_mii_c[127:96]

i_tx_mii_am[3]

o_tx_mii_ready[3]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_c[31:0]

o_rx_mii_am_valid[0]

Port 1:

o_rx_mii_d[511:256]

o_rx_mii_valid[1]

o_rx_mii_c[63:32]

o_rx_mii_am_valid[1]

Port 2:

o_rx_mii_d[767:512]

o_rx_mii_valid[2]

o_rx_mii_c[95:64]

o_rx_mii_am_valid[2]

Port 3:

o_rx_mii_d[1023:768]

o_rx_mii_valid[3]

o_rx_mii_c[127:96]

o_rx_mii_am_valid[3]

Table 48.  Signals of the Fractured MII PCS-only Interface for 200GE-4 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[511:0]

i_tx_mii_valid[3:0]

i_tx_mii_c[63:0]

i_tx_mii_am[3:0]

o_tx_mii_ready[3:0]

o_rx_mii_d[511:0]

o_rx_mii_valid[3:0]

o_rx_mii_c[63:0]

o_rx_mii_am_valid[3:0]

1x 200GE-4

1x 200GE-2

Port 0:

i_tx_mii_d[511:0]

i_tx_mii_valid[0]

i_tx_mii_c[63:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[511:0]

o_rx_mii_valid[0]

o_rx_mii_c[63:0]

o_rx_mii_am_valid[0]

2x 100GE-2

2x 100GE-1

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_c[31:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 2:

i_tx_mii_d[511:256]

i_tx_mii_valid[2]

i_tx_mii_c[63:32]

i_tx_mii_am[2]

o_tx_mii_ready[2]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_c[31:0]

o_rx_mii_am_valid[0]

Port 2:

o_rx_mii_d[511:256]

o_rx_mii_valid[2]

o_rx_mii_c[63:32]

o_rx_mii_am_valid[2]

4x 50GE-1

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid[0]

i_tx_mii_c[15:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[255:128]

i_tx_mii_valid[1]

i_tx_mii_c[31:16]

i_tx_mii_am[1]

o_tx_mii_ready[1]

Port 2:

i_tx_mii_d[383:256]

i_tx_mii_valid[2]

i_tx_mii_c[47:32]

i_tx_mii_am[2]

o_tx_mii_ready[2]

Port 3:

i_tx_mii_d[511:384]

i_tx_mii_valid[3]

i_tx_mii_c[63:48]

i_tx_mii_am[3]

o_tx_mii_ready[3]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_c[15:0]

o_rx_mii_am_valid[0]

Port 1:

o_rx_mii_d[255:128]

o_rx_mii_valid[1]

o_rx_mii_c[31:16]

o_rx_mii_am_valid[1]

Port 2:

o_rx_mii_d[383:256]

o_rx_mii_valid[2]

o_rx_mii_c[47:32]

o_rx_mii_am_valid[2]

Port 3:

o_rx_mii_d[511:384]

o_rx_mii_valid[3]

o_rx_mii_c[63:48]

o_rx_mii_am_valid[3]

2x 50GE-2

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid[0]

i_tx_mii_c[15:0]

i_tx_mii_am

o_tx_mii_ready[0]

Port 2:

i_tx_mii_d[383:256]

i_tx_mii_valid[2]

i_tx_mii_c[47:32]

i_tx_mii_am[2]

o_tx_mii_ready[2]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_c[15:0]

o_rx_mii_am_valid[1:0]

Port 2:

o_rx_mii_d[383:256]

o_rx_mii_valid[2]

o_rx_mii_c[47:32]

o_rx_mii_am_valid[2]

1x 100GE-4

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_c[31:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_c[31:0]

o_rx_mii_am_valid[0]

Table 49.  Signals of the Fractured MII PCS-only Interface for 200GE-2 Reconfigurable GroupFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Top Level Interface Mode TX Interface RX Interface

i_tx_mii_d[511:0]

i_tx_mii_valid[1:0]

i_tx_mii_c[63:0]

i_tx_mii_am[1:0]

o_tx_mii_ready[1:0]

o_rx_mii_d[511:0]

o_rx_mii_valid[1:0]

o_rx_mii_c[63:0]

o_rx_mii_am_valid[1:0]

1x 200GE-2

Port 0:

i_tx_mii_d[511:0]

i_tx_mii_valid[0]

i_tx_mii_c[63:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[511:0]

o_rx_mii_valid[0]

o_rx_mii_c[63:0]

o_rx_mii_am_valid[0]

2x 100GE-1

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_c[31:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[511:256]

i_tx_mii_valid[1]

i_tx_mii_c[63:32]

i_tx_mii_am[1]

o_tx_mii_ready[1]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_c[31:0]

o_rx_mii_am_valid[0]

Port 1:

o_rx_mii_d[511:256]

o_rx_mii_valid[1]

o_rx_mii_c[63:32]

o_rx_mii_am_valid[1]

1x 100GE-2

Port 0:

i_tx_mii_d[255:0]

i_tx_mii_valid[0]

i_tx_mii_c[31:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[255:0]

o_rx_mii_valid[0]

o_rx_mii_c[31:0]

o_rx_mii_am_valid[0]

2x 50GE-1

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid[0]

i_tx_mii_c[15:0]

i_tx_mii_am

o_tx_mii_ready[0]

Port 1:

i_tx_mii_d[383:256]

i_tx_mii_valid[1]

i_tx_mii_c[47:32]

i_tx_mii_am[1]

o_tx_mii_ready[1]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_c[15:0]

o_rx_mii_am_valid[0]

Port 1:

o_rx_mii_d[383:256]

o_rx_mii_valid[1]

o_rx_mii_c[47:32]

o_rx_mii_am_valid[1]

1x 50GE-2

Port 0:

i_tx_mii_d[127:0]

i_tx_mii_valid[0]

i_tx_mii_c[15:0]

i_tx_mii_am[0]

o_tx_mii_ready[0]

Port 0:

o_rx_mii_d[127:0]

o_rx_mii_valid[0]

o_rx_mii_c[15:0]

o_rx_mii_am_valid[0]