Symmetric Cryptographic Intel FPGA Hard IP User Guide

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ID 714305
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives 10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
7. Configuration Registers x
7.1. Cryptographic Primary Control Register 7.2. Cryptographic Secondary Control Register 7.3. Cryptographic Primary Status Register 7.4. Cryptographic Error Status Register 7.5. Cryptographic Error Control Register 7.6. Cryptographic Packet Error Control 1 Register 7.7. Cryptographic Packet Error Control 2 Register 7.8. Cryptographic Error Code Control 1 Register 7.9. Cryptographic Error Code Control 2 Register 7.10. Cryptographic Error Code Internal Control Register 7.11. Cryptographic Internal Error Control Register 7.12. Cryptographic First Error Log Register 7.13. Cryptographic Packet Error Log 1 Register 7.14. Cryptographic Packet Error Log 2 Register 7.15. Cryptographic Internal Error Log Register 7.16. Cryptographic Wall Clock LSB Register 7.17. Cryptographic Wall Clock MSB Register 7.18. Ternary Control Register
8. Design Example x
8.1. Functional Description 8.2. Crypto VSIP Top Block Descriptions 8.3. Test Configurations 8.4. Software Requirements 8.5. Simulation Requirements 8.6. Steps to Generate the Design Example 8.7. Running Simulation Tests 8.8. Running Hardware Tests
8.2. Crypto VSIP Top Block Descriptions x
8.2.1. Clock and Reset 8.2.2. Host Interface
8.7. Running Simulation Tests x
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests x
8.8.1. Supported Boards 8.8.2. Steps to Compile the Design Example for Hardware 8.8.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

7.4. Cryptographic Error Status Register

Table 50.   err Register
Offset 0x14
Addressing Mode 32-bits
Description Cryptographic error status register.
The mem_ecc_derr and mem_ecc_serr registers assert if one or more uncorrectable or correctable memory errors occur on any soft logic. The following procedure loops through all available memories to identify the memory that asserted the ECC error flag:
  • Unset set qualifier mem_ecc_error_qual
  • Select the memory mem_ecc_error_sel[2:0]
  • Set qualifier mem_ecc_error_qual
  • Read status registers mem_ecc_derr and mem_ecc_serr
  • Unset set qualifier mem_ecc_error_qual
  • Clear the mem_ecc_errror status register and set the clear_error register
Table 51.   err Field Description
Bit Name Type Reset Description
31:25 ext R0 0x00 Indicates the extended error status.
  • [31:27]: Reserved
  • [26]: CTS is required but CTS core is not available.
  • [25]: SM4 processing attempt while SM4 is disabled.
24 mem_ecc_derr RO 0x00 Indicates the ECC uncorrectable memory error.
  • Asserts when uncorrectable error occurred on the memory selected with the mem_ecc_error_sel selection bit.
  • Clears when the clear_error register or the clear_all_status register.
23 mem_ecc_serr RO 0x00 Indicates the ECC correctable memory error.
  • Asserts when correctable error occurred on the memory selected with the mem_ecc_error_sel selection bit.
  • Clears when the clear_error register or the clear_all_status register asserts.
22 all_mem_ecc_derr RO 0x00 Indicates the global ECC uncorrectable memory error.
  • Asserts when an ECC uncorrectable error occurred in at least one of the Cryptographic ICA Hard IP following memories:
    • Cryptographic Interface Packetizer
    • Cryptographic Interface Depacketizer
    • Cryptographic Interface Mac FIFO
    • Encryption tweak or IV RAM
    • GHash Key RAM
    • Hash key powers RAM
    • Key1Hi RAM
    • Key1Lo RAM
    • Key2Hi RAM
    • Key2Lo RAM
    • GHash State RAM
    • Reserved
    • Proto state RAM
    • Key ID LUT RAM
    • Y0 Encrypted RAM
  • Clears when the clear_error register or the clear_all_status register asserts.
21 all_mem_ecc_serr RO 0x00 Indicates the global ECC correctable memory error.
  • Asserts when an ECC correctable error occurred in at least one of the Cryptographic ICA Hard IP following memories:
    • Key1Lo RAM
    • Key1Hi RAM
    • Key2Lo RAM
    • Key2Hi RAM
    • Encryption tweak or IV RAM
    • Y0 Encrypted RAM
    • GHash Key RAM
    • HKeyPow RAM1
    • GHash State RAM
    • CNT RAM
    • DFD Hub
    • Cryptographic Interface Depacketizer
    • Cryptographic Interface Packetizer
    • Cryptographic Interface Mac FIFO
  • Clears when the clear_error register or the clear_all_status register asserts.
20 crypto_mode RO 0x00 Indicates the cryptographic mode.
19 direction RO 0x00 Indicates the obfuscation direction:
  • 1: Encryption
  • 0: Decryption
18 key_size RO 0x00 Indicates the size of an en/decryption key:
  • 1: 128-bit key
  • 0: 256-bit key
17:8 channel_id RO 0x00 Indicates the channel ID that contains an error.
7:0 error_code RO 0x00 Indicates the received error code. Available error codes are:
  • [7]: XTS decryption key was loaded but the decrypt key scheduler core is not available.
  • [6]: CTR counter overflow. This error code is available for GCM setting only.
  • [5]: CTS mode was requested but CTS pipeline was bypassed.
  • [4]: Key RAM uncorrectable ECC error
  • [3]: Stream RAM uncorrectable ECC error
  • [2]: SOB without EOB error
  • [1]: Transfer without SOB error
  • [0]: Attempt to load the tweak/IV with first input data word while tweak/IV encryption core is not available.
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