Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/31/2022
Public

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Document Table of Contents

7.5. Cryptographic Error Control Register

Table 52.   pinerr_ctrl Register
Offset 0x24
Addressing Mode 32-bits
Description Cryptographic error control register. Specifies which one of the 32 bit internal errors is OR-ed with the egress error output bit.

Example: A value of 0xFFFFFFFF ORs all 32 errors with the egress error output bit. A value of 0x3 ORs the internal error [0] and internal error [1] with the egress error output bit.

Table 53.   pinerr_ctrl Field Description
Bit Name Type Reset Description
31:0 muxor RW 0xFFFF_FF3F Defines which internal error drives the internal error output pin. The enabled bit(s) are OR-ed together to drive the final output.

The available errors are:

The bits map the corresponding bits in the Internal Error Log register.

This register only affects the output pin, not the CSR error logs.