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8.2.1. Clock and Reset
This block is responsible for generating the required clocks and resets for VSIP and Crypto.
VSIP uses the board clock (100MHz) for driving the VSIP control and status register (CSR) interface and the Symmetric Cryptographic Intel FPGA Hard IP AXI-Lite Interface. Apart from the board clock, the VSIP also generates two more clocks using IOPLLs for the AXI Streaming (AXI-ST) Interface and Symmetric Cryptographic Intel FPGA Hard IP core. The two IOPLLs generating clocks are as follows:
- IOPLL0: AXI-ST clock / VSIP Clock
- IOPLL1: Crypto Core clock
Both IOPLL0 and IOPLL1 use the board clock as the reference clock. The VSIP clock is the same as the AXI-ST clock. By default, the AXI-ST clock and Symmetric Cryptographic Intel FPGA Hard IP Core clock runs at 400 MHz.