F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

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ID 710578
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. TX Tunnel Interface 2.10. Using TX Tunnel Interface 2.11. RX Tunnel Interface 2.12. Using RX Tunnel Interface 2.13. Status Interface for Tunnel Line Rate 2.14. Serial Interface 2.15. CPRI PHY Reconfiguration Interface 2.16. Datapath Avalon Memory-Mapped Interface 2.17. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Sub Profile Parameters Validation
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

2.1.1. Required Clock Frequencies

Table 9.  Required Clock Frequencies
Port Name Frequency (MHz) Notes
i_reconfig_clk 100 Provides CSR access on all the Avalon® memory-mapped interfaces.
o_tx_clkout 402.83203125

415.0390625

451.5625

 System clock divided by 2.
o_tx_clkout2 Generic mode Tunneling mode  
368.64 N/A CPRI PHY system clock for 24G channels.
184.32 N/A CPRI PHY system clock for 12G channels.
153.6 316.8 CPRI PHY system clock for 10G channels.
491.52 307.2 CPRI PHY system clock for 9.8G channels.
307.2 N/A CPRI PHY system clock for 6G channels.
245.76 153.6 CPRI PHY system clock for 4.9G channels.
153.6 N/A CPRI PHY system clock for 3G channels.
122.88 76.8 CPRI PHY system clock for 2.4G channels.
61.44 N/A CPRI PHY system clock for 1.2G channels.
o_rx_clkout 402.83203125

415.0390625

451.5625

 System clock divided by 2
o_rx_clkout2 Generic mode Tunneling mode  
368.64 Not supported Derived from recovered clock for 24G channels.
184.32 N/A Derived from recovered clock for 12G channels.
153.6 316.8 Derived from recovered clock for 10G channels.
491.52 307.2 Derived from recovered clock for 9.8G channels.
307.2 N/A Derived from recovered clock for 6G channels.
245.76 153.6 Derived from recovered clock for 4.9G channels.
153.6 N/A Derived from recovered clock for 3G channels.
122.88 76.8 Derived from recovered for 2.4G channels.
61.44 N/A Derived from recovered clock for 1.2G channels.
i_sampling_clk 250 Sampling clock for deterministic logic from external source.
Level Two Title