F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

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ID 710578
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. TX Tunnel Interface 2.10. Using TX Tunnel Interface 2.11. RX Tunnel Interface 2.12. Using RX Tunnel Interface 2.13. Status Interface for Tunnel Line Rate 2.14. Serial Interface 2.15. CPRI PHY Reconfiguration Interface 2.16. Datapath Avalon Memory-Mapped Interface 2.17. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Sub Profile Parameters Validation
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.12.04 23.4 3.4.0
  • Updated the figure IP Parameter Editor (Figure 5).
  • Added the figure Analog Parameters Tab for Base Profile (Figure 6).
  • Added the figure Analog Parameters Tab for Sub Profile (Figure 7).
  • Added the table Parameter Settings: Analog Parameters Options (Table 25).
2023.08.03 23.2 3.2.1
  • Added support for PMA direct tunneling mode.
  • Updated the register map for tunneling mode support.
  • Added the table Delay Equations for 2.4G/4.9G/9.8G/10G. Tunnel Mode (Table 30) in the Deterministic Latency section.
  • Updated the Sub Profile Availability table.
  • Updated the Block Diagram.
  • Updated the product family name to "Intel Agilex 7."
2022.03.28 22.1 2.1.0
  • Removed support for ModelSim* SE simulator.
  • Added new parameter: Enable CDR Clock Output.
  • Added new sections:
    • CDR Clock Output
    • RX PMA Adaptation
2022.02.04 21.4 2.0.0 Initial release.
Level Two Title