F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

ID 710578
Date 12/04/2023
Public
Document Table of Contents

2.7. RX Interface (8b/10b)

The RX 8b/10b interface is available only if you enable the Enable reconfiguration to 8b/10b datapath parameter or if you select the 8b/10b CPRI line rate. For the CPRI PHY core to power up in the 64b/66b line rate, the IP core asserts these signals when you reconfigure the core at runtime to enter the 8b/10b line rate.

Table 15.  RX 8b/10b Interface
Port Name Width (Bits) Domain Description
i_rx_d[15:0] 16 o_rx_clkout2 Indicates 8b/10b RX data for the corresponding CPRI PHY channel.
i_rx_c[1:0] 2 o_rx_clkout2 Indicates 8b/10b RX control for the corresponding CPRI PHY channel.
When you transmit the data using the RX 8b/10b interface:
  • The frames are 8b/10b encoded. Each byte in i_rx_d has a corresponding bit in i_rx_c that indicates whether the byte is a control byte or a data byte. For example, i_rx_c[0] is the control bit for i_rx_d[7:0].
  • The byte order for the RX interface flows from right to left and the first byte that the core receives is i_rx_d[7:0].
  • The first bit that the core receives is i_rx_d[0].