2.5.3. Top-Level Common Blocks
The CPU subsystem functions as SCDC and DDC controllers, and source reconfiguration controller.
|F-Tile Reference and System PLL Clock||
This IP connects the System PLL output clock as well as the Tx PLL and Rx CDR reference clock to the F-tile PMA/FEC Direct PHY IP.
System PLL clock output shall always set to run at a higher clock frequency than the native PMA recovered clock.
For this design, the clock frequency is 900 MHz.
In F-Tile HDMI Intel FPGA IP Design Example, F-Tile Reference and System PLL Clock IP is configured to enable out_coreclk_1 which is driven by Refclk #1 for FGT PMA.
The F-Tile Reference and System PLL Clock IP configuration for the reference clock routed to the core feature in this design example is limited only for the HDMI application. For more information about the supported mode and configuration of the IP, refer to the Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP section of the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.
|Transceiver Reconfig Arbiter||
|Dynamic Reconfig IP||
HDMI example design using Dynamic Reconfiguration (DR) IP to reconfigure dynamically is a subset of the transceiver channels to operate in different modes (e.g. data rates) without impacting the adjacent active channels.