F-Tile HDMI Intel® FPGA IP Design Example User Guide

ID 709314
Date 10/02/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

2.1. Design Features

The design example supports the following features:
  • HDMI configuration of:
    • 8 pixel-in-parallel in video domain
    • 8 symbols per clock in FRL domain
  • FRL mode only
  • EDID passthrough mode only