2.5.1. HDMI TX Components
|HDMI TX Core||
The IP receives video data from the top level and performs auxiliary data encoding, audio data encoding, video data encoding, scrambling, TMDS encoding or packetization.
|IOPLL (pll_frl_tx)||The IOPLL (pll_frl_tx) generates the FRL clock for the TX core. This reference clock receives the TX FPLL output clock.
FRL clock frequency = Data rate per lanes x 4 / (FRL characters per clock x 18)
|IOPLL (pll_cadence_tx)||The IOPLL generates the clock for the tx_cadence_slow_clk in the TX transceiver to generate the tx_cadence. Since there is a conversion of the data width from 40bit from TX core to 64 bits in TX transceiver, the tx_cadence_slow_clk needs to be supplied with a clock derived from transceiver output clock with the frequency 5/8*Tx transceiver clock frequency.|
|TX PMA Direct PHY||
Hard transceiver block that receives the parallel data from the HDMI TX core, serializes the data and transmits it.
|Output buffer||This buffer acts as an interface to interact the I2C interface of the HDMI DDC and redriver components.|
|80b to 128b Converter||Convert 80 bits input to the 128 bits output to be accepted by the transceiver TX.|
|DCFIFO||Synchronize data and signals across the System clock and TX clock domains.|
|TX Reconfig Management||
In TMDS mode, the TX reconfiguration management block reconfigures the TX Transceiver for different output clock frequency according to the TMDS clock frequency of the specific video.
In FRL mode, the TX reconfiguration management block reconfigures the TX Transceiver to supply the serial fast clock for 3 Gbps, 6 Gbps, 8 Gbps, 10 Gbps and 12 Gbps according to FRL_Rate field in the 0x31 SCDC register.
The TX reconfiguration management block switches the TX Transceiver reference clock between reference clock 1 for TMDS mode and reference clock 0 for FRL mode.
|F-tile Reference and System PLL Clock IP||F-tile Reference and System PLL Clock IP has two reference clocks: