AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines
ID
709310
Date
6/21/2022
Public
1. Terms and Acronyms
Updated for: |
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Intel® Quartus® Prime Design Suite 22.2 |
Term | Definition |
---|---|
ALA | Advanced Link Analyzer |
ATXPLL | ATX Phase Lock Loop |
BUJ | Bounded, Uncorrelated Jitter |
CTS | Compliance Test Suite |
DDC | Display Data Channel |
DJ | Deterministic Jitter |
ESD | Electrostatic Discharge |
FMC | FPGA Mezzanine Connector |
FPLL | Fractional Phase Lock Loop |
FR4 | PCB dielectric material |
FRL | Fixed Rate Link |
PCA | Power over Cable Assembly |
PCB | Printed Circuit Board |
PJ | Periodic Jitter |
QSF | Quartus Settings File |
RJ | Random Jitter |
Rogers | PCB dielectric material |
SDG | System Design Guidelines |
SJ | Sinusoidal Jitter |
TI | Texas Instruments |
TMDS | Transition Minimized Differential Signaling |
TP1 | Test Point 1 |
TTK | Transceiver Toolkit |
TTM | Time to Market |
Vpp | Peak-to-Peak Voltage |
WCM | Worsecase Cable Model |
Z | Impedance |