4.3.1. FPGA TX Settings
Intel recommends the settings in Table 6 for your FPGA TX. Both FPLL and ATXPLL apply. In general, ATX PLL has a slightly better margin than FPLL, although this may not be a dominant factor for Intel® Arria® 10 and Intel® Stratix® 10.
For a complete list of settings, refer to Transceiver User Guide.
|Vod output swing ctrl||30|
|Pre emp sign 1st post tap||Fir post 1t neg|
|Pre emp sign 2nd post tap||Fir post 2t neg|
|Pre emp switching ctrl 1st post tap||5|
|Pre emp switching ctrl 2nd post tap||0|
|Pre emp sign pre tap 1t||Fir pre 1t post|
|Pre emp sign pre tap 2t||Fir pre 2t neg|
|Pre emp switching ctrl pre tap 1t||0|
|Pre emp switching ctrl pre tap 2t||0|
|Slew rate ctrl||Slew r5|
Set TX slew rate to r5 to ensure all four TMDS data channels (three data channels and one clock) are within the 2 UI bonding requirements of Test Point 1 (TP1) and meet inter-lane skew requirements.
Your TX redriver settings are determined by your PCB design profile. Intel recommends a minimum VOD setting of 1.0 on the TX redriver.