AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

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ID 709310
Date 6/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Prerequisites and Scope 4. System Design Guidelines Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines
4. System Design Guidelines Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practices 4.3. System Link Budgeting Recommendations
4.3. System Link Budgeting Recommendations x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
4.3.2. FPGA RX Settings x
4.3.2.1. Intel® Stratix® 10-specific RX Feature
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Performance and Cost Considerations
6. Future System Level Optimization x
6.1. Availability of Redrivers or Retimers 6.2. The Intel Agilex® Platform
1. Terms and Acronyms
2. Introduction
3. Prerequisites and Scope
4. System Design Guidelines Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

4.1. Enabling PCB panel design

The following guidelines and requirements target general PCB panels. You can use FR4 stack-up to reduce costs or Rogers for better signalling on larger panels. Evaluate your stack-up requirements based on the attributes in the table below.

Ensure that your cables meet HDMI 2.1 certification. HDMI.org provides a list of compliant connectors and cables along with their providers. For the purpose of this guide, Intel uses Belkin cables with HDMI IP running 12-gigabits per second (Gbps) Fixed Rate Link (FRL).

Table 2.  Summary of daughtercard PCB general design guidelines
Item Impedance (Z)/Length Type/Stack-up Comment
Trace 90-100 Ω Length matched FR4, microstrip top/bottom layer Keep stack-up targeting 90 Ω; to minimize reflection loss
Connectors & Cables 95 Ω Surface mount Use compliant connectors such Belkin HDMI 2.1 cables
Components 90 Ω Surface mount Reduce void by placement optimization
Power plane NA

Lowest Z possible

 2 layers Partial to full Ground reference; full reference whenever possible
Ground plane Lowest plane Z NA Full reference for signals

HDMI 2.1 accommodates both Transition Minimized Differential Signaling (TMDS) and Fixed Rate Link (FRL) modes.

  • TMDS supports legacy HDMI devices running on three data lanes and one clock lane.
  • FRL runs on four data lanes.

On the receiver (RX), the TMDS clock path shares the FRL data lane.Therefore, on the PCB panel with Intel FPGA, you need a fanout buffer to split incoming RX signals to drive both paths to support both TMDS and FRL. At the schematic design level, one approach is to use an external fanout buffer. However, this additional fanout buffer increases system costs. Another approach is to use an integrated fanout buffer option with redriver at the RX side to recover signals at 19-decibel (dB) up to 12 Gbps.

HDMI 2.1 operates up to 12 Gbps with cable loss of up to 16dB. For cost optimization, use the redriver at the transmitter side.

The table below shows a summary of the redrivers for Intel® Arria® 10 and Intel® Stratix® 10.
Table 3.  Redriver loss compensation and attributes
Component

(TI redrivers)

 Insertion loss @12 Gbps Z Comment
DS125BR820 10dB 90 Ω TX redriver
DS125MB203 18dB 90 Ω RX redriver, integrated Fanout buffer
Intel recommends trace impedance (Z) target to be in range 90-100 Ω; do not exceed 100 Ω (not considering fabrication tolerance). This ensures best possible reach on both trace length and signal integrity
Figure 2. Daughtercard panel size
Note: The reference design uses FR4 material due to it is low cost.

The daughtercard panel size is small with high speed traces within 10 inches. If you target larger margin and desire for larger panel, you can opt for Meg6 material. Intel recommends a flex cable topology for signals up to 12 Gbps.

For design with 4 layer (SGPS) FR4 stackup, refer below parameters for microstrip/top layer:
Table 4.  FR4 Stack-up Target
Type FR4 Thick (T) um Width (W) um Height (H) um Spacing (S) um Dieletric Constant (Dk)
Zdiff=100 Ω 35 203.2 110 100 4.3
Note: Z target is 90 to 100 Ω
Figure 3 illustrates the parameters:
Figure 3. PCB fabrication Cross-section Attributes
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