F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 6/27/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

5.6.2. Multi-Device ADC Application for Subclass 1

Similar to Subclass 1 DAC scheme, the SYSREF is the reference timing that starts the LEMC counters in both converter devices and logic device (FPGA).
In this mode, the RX IP is required to synchronize the following two events of the RX IPs:
  1. EMB Locked
  2. Lane Deskew Completed
By having each RX IP synchronizing to these two events, all RX IP data can align, and hence achieve the desired synchronization behavior while meeting its deterministic nature against SYSREF.
Figure 11. Multi-Device ADC Synchronization