F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 6/27/2023

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5.5. Interrupt and Error Handling

The F-Tile JESD204C IP interrupts the processor when there are errors or reinitialization requests in the design. The interrupts are peripheral and level sensitive.

The IP holds a level-sensitive interrupt signal asserted until the peripheral deasserts the interrupt signal. When the level-sensitive interrupt is high, the state of the interrupt in the Interrupt Controller is pending or active pending. If the peripheral deasserts the interrupt signal for any reason, the Interrupt Controller removes the pending state from the interrupt.

Every error condition in the F-Tile JESD204C IP latches on the error status and keeps the interrupt signal asserted until the error is serviced and the ISR writes a 1 to clear the error status.

When interrupt is asserted and fulfills the Interrupt Controller configuration (for example, priority, interrupt IDs), the processor jumps to the Interrupt Service Routine (ISR) to execute the routine.

The ISR must service the requirements of the F-Tile JESD204C IP by reading the error status and then clearing the interrupt, so that the F-Tile JESD204C IP could deassert the interrupt. This is particularly important for level-sensitive interrupts, where ISR must ensure that the interrupt is deasserted at the Interrupt Controller input before proceeding to the next step. Typically, this is called the top half ISR handler.

The bottom half ISR handler may require a chain of events.