F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 6/27/2023

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3.3. CRC Encoding/Decoding

The F-Tile JESD204C IP supports only CRC-12 encoding/decoding.

The CRC-12 encoder computes 12 parity bits using this polynomial:

0 x 987 = x12 + x9 + x8 + x3 + x2 + x1 + 1