3.2.1. LEMC Counter
F-Tile JESD204C IP maintains an LEMC counter that counts from 0 to (E*32)–1 and wraps around again.
In Subclass 0 system, the LEMC counter starts at the deassertion of the link reset signal, without waiting for SYSREF detection.
In Subclass 1 deterministic latency system, all transmitters and receivers receive a common SYSREF, and the LEMC counter resets within two link clock cycles. SYSREF must be the same for the converter devices, which are grouped and required to be synchronized together.
Maximum SYSREF frequency = data rate/(66x32xE).
|ADC Group 1 (2 ADCs)||
||(6,000 MHz/(66x32x2) = 1.42 MHz|
|ADC Group 2 (2 ADCs)||
||(6,000 MHz/(66x32x1) = 2.84 MHz|
|DAC Group 3 (2 DACs)||
||(3,000 MHz/(66x32x1) = 1.42 MHz|