5.1. Understanding the Design Steps for CvP Initialization Mode

Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

Download PDF

ID 683889

Date 9/04/2020

Version current

Public

Document Table of Contents

Document Table of Contents x

1. Overview 2. FPGA Configuration using CvP 3. CvP Topologies 4. Design Considerations 5. CvP Example Designs 6. CvP Driver and Registers 7. Document Revision History for the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

1. Overview x

1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes 1.4. CvP Revision Design Flow 1.5. CvP Topologies 1.6. Additional Information about PCI Express

2. FPGA Configuration using CvP x

2.1. CvP Configuration Images 2.2. CvP Modes 2.3. Alternative to CvP Initialization: Autonomous HIP Mode 2.4. CvP Compression and Encryption Features 2.5. Core Image Update 2.6. CvP Pins

2.2. CvP Modes x

2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode

2.4. CvP Compression and Encryption Features x

2.4.1. Data Compression 2.4.2. Data Encryption

3. CvP Topologies x

3.1. Single Endpoint 3.2. Multiple Endpoints 3.3. Mixed Chain

3.3. Mixed Chain x

3.3.1. Configuring Slave FPGAs with Different Configuration Files 3.3.2. Configuring Slave FPGAs with a Single Configuration File

4. Design Considerations x

4.1. Preparing the Design for CvP Revision Design Flow 4.2. Designing CvP for an Open System 4.3. Designing CvP for a Closed System 4.4. Clock Connections for CvP Designs Including the Transceiver Reconfiguration Controller

4.2. Designing CvP for an Open System x

4.2.1. FPGA Power Supplies Ramp Time Requirement 4.2.2. PCIe Wake-Up Time Requirement

4.2.2. PCIe Wake-Up Time Requirement x

4.2.2.1. PCIe Wake-Up Time Requirement for CvP Initialization Mode 4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode

4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode x

4.2.2.2.1. Recommended Configuration Schemes 4.2.2.2.2. Estimating PCIe Wake-Up Time Requirement

5. CvP Example Designs x

5.1. Understanding the Design Steps for CvP Initialization Mode 5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow 5.3. Understanding the Design Steps for CvP Update Mode 5.4. Bringing Up the Hardware 5.5. CvP Debugging Check List 5.6. Known Issues and Solutions

5.1. Understanding the Design Steps for CvP Initialization Mode x

5.1.1. Downloading and Generating the High Performance Reference Design 5.1.2. Setting up CvP Parameters for CvP Initialization Mode 5.1.3. Compiling the Design for the CvP Initialization Mode 5.1.4. Splitting the SOF File for the CvP Initialization Design Mode

5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow x

5.2.1. Downloading and Generating the High Performance Reference Design 5.2.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5.2.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region 5.2.4. Setting up CvP Parameters for CvP Initialization Mode 5.2.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5.2.6. Compiling both the Base and cvp_app Revisions in the CvP Revision Design Flow 5.2.7. Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design Flow

5.3. Understanding the Design Steps for CvP Update Mode x

5.3.1. Downloading and Generating the High Performance Reference Design 5.3.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core 5.3.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region 5.3.4. Setting up CvP Parameters for CvP Update Mode 5.3.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow 5.3.6. Compiling the Design for the CvP Update Mode 5.3.7. Splitting the SOF File for the CvP Update Design Mode 5.3.8. Splitting the SOF File for the CvP Update Mode with the CvP Revision Design Flow

5.4. Bringing Up the Hardware x

5.4.1. Installing Jungo WinDriver in Windows Systems 5.4.2. Installing Jungo WinDriver in Linux Systems 5.4.3. Installing Open Source CvP Driver in Linux System 5.4.4. Modifying MSEL for Active Serial x4 Flash on Stratix V Dev-Kit 5.4.5. Programming CvP Images and Validating the Link

5.6. Known Issues and Solutions x

5.6.1. Using MSI-X in CvP Initialization Mode

6. CvP Driver and Registers x

6.1. CvP Driver Support 6.2. CvP Driver Flow 6.3. VSEC Registers for CvP

6.3. VSEC Registers for CvP x

6.3.1. Altera-defined Vendor Specific Capability Header Register 6.3.2. Altera-defined Vendor Specific Header Register 6.3.3. Altera Marker Register 6.3.4. CvP Status Register 6.3.5. CvP Mode Control Register 6.3.6. CvP Data Registers 6.3.7. CvP Programming Control Register 6.3.8. Uncorrectable Internal Error Status Register 6.3.9. Uncorrectable Internal Error Mask Register 6.3.10. Correctable Internal Error Status Register 6.3.11. Correctable Internal Error Mask Register

1. Overview

1.1. Benefits of Using CvP

1.2. CvP System

1.3. CvP Modes

1.4. CvP Revision Design Flow

1.5. CvP Topologies

1.6. Additional Information about PCI Express

2. FPGA Configuration using CvP

2.1. CvP Configuration Images

2.2. CvP Modes

2.2.1. CvP Initialization Mode

2.2.2. CvP Update Mode

2.3. Alternative to CvP Initialization: Autonomous HIP Mode

2.4. CvP Compression and Encryption Features

2.4.1. Data Compression

2.4.2. Data Encryption

2.5. Core Image Update

2.6. CvP Pins

3. CvP Topologies

3.1. Single Endpoint

3.2. Multiple Endpoints

3.3. Mixed Chain

3.3.1. Configuring Slave FPGAs with Different Configuration Files

3.3.2. Configuring Slave FPGAs with a Single Configuration File

4. Design Considerations

4.1. Preparing the Design for CvP Revision Design Flow

4.2. Designing CvP for an Open System

4.2.1. FPGA Power Supplies Ramp Time Requirement

4.2.2. PCIe Wake-Up Time Requirement

4.2.2.1. PCIe Wake-Up Time Requirement for CvP Initialization Mode

4.2.2.2. PCIe Wake-Up Time Requirement for CvP Update Mode

4.2.2.2.1. Recommended Configuration Schemes

4.2.2.2.2. Estimating PCIe Wake-Up Time Requirement

4.3. Designing CvP for a Closed System

4.4. Clock Connections for CvP Designs Including the Transceiver Reconfiguration Controller

5. CvP Example Designs

5.1. Understanding the Design Steps for CvP Initialization Mode

5.1.1. Downloading and Generating the High Performance Reference Design

5.1.2. Setting up CvP Parameters for CvP Initialization Mode

5.1.3. Compiling the Design for the CvP Initialization Mode

5.1.4. Splitting the SOF File for the CvP Initialization Design Mode

5.2. Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow

5.2.1. Downloading and Generating the High Performance Reference Design

5.2.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core

5.2.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region

5.2.4. Setting up CvP Parameters for CvP Initialization Mode

5.2.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow

5.2.6. Compiling both the Base and cvp_app Revisions in the CvP Revision Design Flow

5.2.7. Splitting the SOF File for the CvP Initialization Mode with the CvP Revision Design Flow

5.3. Understanding the Design Steps for CvP Update Mode

5.3.1. Downloading and Generating the High Performance Reference Design

5.3.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core

5.3.3. Creating an Alternate user_led.v File for the Reconfigurable Core Region

5.3.4. Setting up CvP Parameters for CvP Update Mode

5.3.5. Creating CvP Revisions of the Core Logic Region Using the CvP Revision Design Flow

5.3.6. Compiling the Design for the CvP Update Mode

5.3.7. Splitting the SOF File for the CvP Update Design Mode

5.3.8. Splitting the SOF File for the CvP Update Mode with the CvP Revision Design Flow

5.4. Bringing Up the Hardware

5.4.1. Installing Jungo WinDriver in Windows Systems

5.4.2. Installing Jungo WinDriver in Linux Systems

5.4.3. Installing Open Source CvP Driver in Linux System

5.4.4. Modifying MSEL for Active Serial x4 Flash on Stratix V Dev-Kit

5.4.5. Programming CvP Images and Validating the Link

5.5. CvP Debugging Check List

5.6. Known Issues and Solutions

5.6.1. Using MSI-X in CvP Initialization Mode

6. CvP Driver and Registers

6.1. CvP Driver Support

6.2. CvP Driver Flow

6.3. VSEC Registers for CvP

6.3.1. Altera-defined Vendor Specific Capability Header Register

6.3.2. Altera-defined Vendor Specific Header Register

6.3.3. Altera Marker Register

6.3.4. CvP Status Register

6.3.5. CvP Mode Control Register

6.3.6. CvP Data Registers

6.3.7. CvP Programming Control Register

6.3.8. Uncorrectable Internal Error Status Register

6.3.9. Uncorrectable Internal Error Mask Register

6.3.10. Correctable Internal Error Status Register

6.3.11. Correctable Internal Error Mask Register

7. Document Revision History for the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

5.1. Understanding the Design Steps for CvP Initialization Mode

CvP initialization mode divides the design into periphery and core images. The periphery image can be stored in a local flash device on the PCB and the user can program the periphery via Active Serial (AS) mode. The core image is stored in host memory. You must download the core image to the FPGA using the PCI Express link.

Note: If you plan to create multiple versions of the core logic for the same periphery I/O, the new core images must work with the previous periphery image. Refer to Understanding the Design Steps for CvP Initialization Mode with the Revision Design Flow for information about how to create reconfigurable images that connect to the same periphery image.

You must specify CvP initialization mode in the Quartus Prime software by selecting the CvP Settings Core initialization and update. You might choose CvP initialization mode for any of the following reasons: