Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

6.3.1. Altera-defined Vendor Specific Capability Header Register

Table 27.  Altera-defined Vendor Specific Capability Header Register (Byte Offset: 0x200)
Bits Name Reset Value Access Description
[15:0] PCI Express Extended Capability ID 0x000B RO PCIe specification defined value for VSEC Capability ID.
[19:16] Version 0x1 RO PCIe specification defined value for VSEC version.
[31:20] Next Capability Offset Variable RO Starting address of the next Capability Structure implemented, if any.