E-Tile Hard IP Intel Agilex® 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 5/26/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Running the Simulation with Default HEX File

You can run and simulate the default Nios® II-based testbench of the design example using a pre-generated HEX file (nios_system_onchip_memory2_0_ onchip_memory2_0.hex) that provided in the <design_example_dir>/example_testbench directory.
Note: The HEX file is generated based on the C-code design example simulation source files in the dynamic_reconfiguration_sim folder. If you modify the source files, you need to generate a new HEX file using Nios® II Software Build Tools (SBT) for Eclipse. Refer to the Running the Simulation with New HEX File section for the steps on generating a new HEX file and simulating the testbench using the new HEX file.

Follow these steps to simulate the testbench:

  1. Open the <simulator_name>_files.tcl script in the <design_example_dir>/<design_example_dir>/ex_100G/sim/common directory.
  2. Edit the TCL script to change the existing nios_system_onchip_memory2_0_onchip_memory2_0.hex file directory to the pre-generated HEX file directory.
    For example, change the following line in the TCL script from:
    lappend memory_files "[normalize_path "$QSYS_SIMDIR/../<design_example_dir>/hardware_test_design/ip/nios_system/nios_system_onchip_memory2_0/altera_avalon_onchip_memory2_191/sim/nios_system_onchip_memory2_0_onchip_memory2_0.hex"]"
    lappend memory_files "[normalize_path "$QSYS_SIMDIR/../<design_example_dir>/software/dynamic_reconfiguration_sim/nios_system_onchip_memory2_0_onchip_memory2_0.hex"]"
  3. Using the supported simulator of your choice, change to the testbench simulation directory to <design_example_dir>/example_testbench/ <simulator_name>.
  4. Run the simulation script for the simulator. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
  5. Analyze the results. The successful testbench performs the dynamic reconfiguration (DR) operations, sends and transmits packets for each DR operation, and displays "Nios has completed its transactions" and "Simulation PASSED" after completing the simulation.
    Table 27.  Steps to Simulate the Testbench
    Simulator Instructions
    ModelSim* SE or QuestaSim* In the command line, type vsim -do run_vsim.do

    If you prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do run_vsim.do

    Note: The Questa* Intel® FPGA Edition simulator does not have the capacity to simulate this IP core. You must use ModelSim* SE or QuestaSim* .
    Xcelium* In the command line, type sh run_xcelium.sh
    VCS* / VCS* MX In the command line, type sh run_vcs.sh or sh run_vcsmx.sh
    Note: run_vcs.sh is only available if you select Verilog as the Generated HDL Format. If you select VHDL as the Generated HDL Format, you must simulate the testbench with a mixed language simulator using run_vcsmx.sh.
    Note: For Nios® II-based testbench, the simulation runs for more than 5 hours.