E-Tile Hard IP Intel Agilex® 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 5/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.3.3. Performing the Link Initialization

The link initialization is part of the default simulation test. You should perform link initialization before each simulation test. The default HEX file provided for the simulation contains this step.

Follow these steps to perform link initialization:
  1. Wait for PIO_OUT[0] (o_ehip_ready) goes high.
  2. Enable PMA loopback.
  3. Wait for PIO_OUT[3:0] = 0xF (o_tx_ptp_ready, o_sl_rx_pcs_ready, o_sl_rx_block_lock, and o_ehip_ready asserted).
  4. Continuously send packets to the clock data recover (CDR) receiver (RX) deskew training and wait until PIO_OUT[4] (o_rx_ptp_ready goes high.
  5. Clear Ethernet statistic counters.
  6. Enable the packet generator to start sending packets of data. Check the transmitter (TX) packet count statistic counter to confirm all packets are sent.
  7. Check that the packet generator received all expected packets. Confirm the checker_pass status and wait for PIO_OUT[3:0] = 0xF (checker_pass, o_sl_rx_pcs_ready, o_sl_rx_block_lock, and o_ehip_ready asserted).
  8. Disable the packet generator to stop sending packets.

Did you find the information on this page useful?

Characters remaining:

Feedback Message