E-Tile Hard IP Intel Agilex® 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 5/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.6. Document Revision History for the E-tile Dynamic Reconfiguration Design Example

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.04.03 22.4 23.0.0
  • Added the following macro to the simulation run script in the Fast Sim Model for E-tile Ethernet IP for Intel Stratix 10 FPGA.
    +define+CR3TOP_SIMPLE_SERDES
  • Added additional information in 100G Ethernet Dynamic Reconfiguration Design Example.
    • When a CSR reset occurs during or after a dynamic reconfiguration transition(DR), You must perform the DR transition to the base operation mode. Otherwise, the error may occur during the DR transition to other supported configurations.
  • Updated the product family to "Intel Agilex 7".
2022.09.26 22.3 22.0.0
  • Added support for the following in 100G Ethernet Dynamic Reconfiguration Design Example:
    • 100G MAC+PCS+(544,514)RS-FEC [PAM4]
    • 100G MAC+PCS+(544,514)RS-FEC [NRZ]
  • Added additional information regarding 100G Ethernet Dynamic Reconfiguration Design Example with internal and external CPU.
2022.05.20 21.3 20.2.0
  • Updated the E-Tile Dynamic Reconfiguration 100G Ethernet Design Example Directory Structure table.
  • Added the folder design_example_dir>/software/dynamic_reconfiguration_sim
2021.12.11 21.3 20.2.0
  • Added support for Questa simulator.
  • Removed support for NCSim simulator.
  • Added new sections:
    • Dynamic Reconfiguration Flow for 25GbE PTP FEC to 25GbE PTP Non-FEC
    • Dynamic Reconfiguration Flow for 24G CPRI FEC to 24G CPRI Non-FEC
    • Dynamic Reconfiguration Flow for 25GbE PTP FEC to 24G CPRI FEC
    • Steps to Enable FEC
    • Steps to Disable FEC
2020.06.29 20.2 20.2.0
  • Added support for dynamic reconfiguration (DR) transitions from high speed CPRI protocol to low PMA-D modes in 25G Ethernet to CPRI Dynamic Reconfiguration Design Example:
    • 24G CPRI with RS-FEC to 10G CPRI
    • 10G CPRI to 9.8G CPRI
    • 9.8G CPRI to 4.9G CPRI
    • 4.9G CPRI to 2.4G CPRI
    • 2.4G CPRI to 24G CPRI with RS-FEC

    Updated DR simulation test sequence and DR hardware test GUI display with the added transitions.

  • Added dl_reset signal in the CPRI PHY Soft Registers table. The reset acts as a soft reset to the deterministic latency block.
2020.04.13 20.1 19.2.0
  • Added support for deterministic latency feature in the 25G Ethernet to CPRI protocol.
    • Updated the Clocking Scheme for 24G CPRI with RS-FEC Dynamic Reconfiguration Design Example figure.
    • Updated the Simulation Block Diagram for 25G Ethernet to CPRI Dynamic Reconfiguration Design Example figure.
    • Updated components described in the 25GE MAC+PCS with RS-FEC and PTP to CPRI Hardware Dynamic Reconfiguration Design Example Components section.
    • Added CPRI PHY soft registers table in the 25G Ethernet to CPRI Design Examples Registers section.
  • Updated Clock Control frequency setting in the Testing the E-tile Dynamic Reconfiguration Hardware Design Example section. This setting applies to CPRI and Ethernet to CPRI protocols.
  • Updated TEST_MODE selection in the 10GE/25GE MAC+PCS with RS-FEC Simulation Dynamic Reconfiguration Design Example Components section. TEST_MODE options are 0, 1, and 2.
2019.12.30 19.4 19.4.0
  • Added new PMA adaptation flow for 10G/25G variant.
  • Added simulation, compilation, and hardware support for Intel Agilex® 7 dynamic reconfiguration design examples for CPRI protocols:
    • 24G CPRI with RS-FEC
    • 9.8G CPRI with RS-FEC
  • Added simulation, compilation, and hardware support for Intel Agilex® 7 dynamic reconfiguration design examples for 100G Ethernet protocol
2019.10.18 19.3 19.3.0 Initial release.