E-Tile Hard IP Intel Agilex® 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 5/26/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Clocking Scheme

Figure 32. Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC and PTP Dynamic Reconfiguration Design Example
Figure 33. Clocking Scheme for 10G/25GE MAC+PCS with RS-FEC Dynamic Reconfiguration Design Example
Note: i_channel_PLL module is E-tile Transceiver PHY specific module that utilizes additional transceiver E-tile channel.