AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
ID
683856
Date
9/24/2018
Public
1.1. Reference Design Overview
1.2. Getting Started
1.3. Reference Design Components
1.4. Compiling the Reference Design
1.5. Testing the Reference Design
1.6. Extending the Reference Design with Custom Persona
1.7. Document Revision History for AN 784: Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.3.1.3.4. Partial Reconfiguration Logic
The reference design provides the following personas:
Each persona has an 8-bit persona_id field in the pr_data register to indicate a unique identification number. A 32-bit control register and 16 I/O registers follow the 8-bit persona_id. The 16 I/O registers are 32-bit each, with 8 bits for device inputs, and 8 bits for device outputs. Each persona uses these registers in different ways. For more information, refer to the source code for each of the personas.
Persona | Description |
---|---|
DDR4 access | Performs a sweep across a memory span, first writing, and then reading each address. |
Basic DSP | Provides access to a 27x27 DSP multiplier, and demonstrates hardware acceleration. |
Basic arithmetic | Includes a basic 32-bit unsigned adder, and demonstrates hardware acceleration. |
Game of Life | Includes an 8x8 Conway's Game of Life, and demonstrates hardware acceleration. |
Additionally, the reference design provides a template to implement your custom persona. This template persona allows you modify the RTL, create a wrapper to interface with the register file, compile, and run your design.